Page interleaved memory access

• US 5,051,889 A
• Filed: 03/07/1990
• Issued: 09/24/1991
• Est. Priority Date: 10/23/1987
• Status: Expired due to Fees

• Current Assignee: Chips and Technologies, Inc. (Intel Corporation)
• Original Assignee: Chips and Technologies, Inc. (Intel Corporation)
• Inventors: Wang, Justin, Fung, Michael G.
• Primary Examiner(s): Hecker, Stuart N.
• Assistant Examiner(s): Rudolph, Rebecca L.
• Application Number:
  US07/490,023
• Time in Patent Office: 566 Days
• Field of Search: 364/200, 364/900, 365/230.03, 365/230.04
• US Class Current: 711/157
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/1615 using a concurrent pipeline structrure
• CPC Class Codes: G06F 13/1631 through address comparison

Abstract

The present invention provides a memory organization scheme for a high-performance memory controller. The memory organization of the present invention combines page mode techniques and interleaving techniques to achieve high-performance.

Sequential pages of memory are interleaved between memory banks so that memory accesses which are a page apart will be to two different memory banks. A page is preferably defined by a single row, with 2K columns per row defining the number of bits in a page. Accesses to bits in the same page as a previous access omit the row pre-charge cycle, thus speeding up the memory cycle. Accesses to a separate bank of memory chips from the previous access are likewise speeded up since there is no need to wait for the completion of the cycle in the previous bank before initiating the cycle in the separate bank.

Claims

1. A memory controller for providing address and timing signals to at least two banks of DRAM memory chips, each of said DRAM memory chips being one of a predetermined, limited range of sizes, comprising:

an input address bus including a plurality of bit lines forming a bank address, column address, a row address and at least one page select address bit input connected at a less significant bit than the least significant bit of said row address for a smallest one of said DRAM chip sizes;

a first last row register having inputs coupled to said row address bit lines of said input address bus;

a second last row register having inputs coupled to said row address bit lines of said address bus;

first comparator means having a first input coupled to said row address bit lines of said input address bus and a second input coupled to an output of said first register;

second comparator means having a first input coupled to said row address bit liens of said input address and a second input coupled to an output of said second register;

a page select address bit line coupled between said page select bit input and an enabling input of each of said first and second comparator means, such that only one of said comparator means is activated in response to a bit on said page select address bit line;

logic state machine means having an input coupled to comparator outputs of said first and second comparator means for producing a first timing cycle with a row address pulse and then a column address pulse responsive to a first state of said comparator outputs and for producing a second timing cycle with only a column address pulse in response to a second state of said comparator outputs when a current row address matches a last row address, said second timing cycle being shorter in duration than said first timing cycle, said timing cycles being provided to a first one of said banks responsive to said output of said first comparator means and to a second one of said banks responsive to said output of said second comparator means, such that interleaving between said banks is controlled by said page select address bit enabling one of said comparator means;

a configuration register for indicating the location of said banks of memory in a memory address space; and

address comparison means, having a first input coupled to said configuration register and a second input coupled to said input address bus, for comparing bank address bits of said input address bus to said location of said banks of memory and providing an enable signal to said logic state machine means when said input address is within said location.

2. The memory controller of claim 1 wherein said page select address bit and said input address are addresses from an external processor before being translated to a physical address.