Simulation of selected logic circuit designs

• US 5,051,938 A
• Filed: 06/23/1989
• Issued: 09/24/1991
• Est. Priority Date: 06/23/1989
• Status: Expired due to Term

• Current Assignee: Stanley M. Hyduke
• Original Assignee: Stanley M. Hyduke
• Inventors: Hyduke, Stanley M.
• Primary Examiner(s): Dixon, Joseph L.
• Application Number:
  US07/370,896
• Time in Patent Office: 823 Days
• Field of Search: 364/578, 364/488-490, 364/550, 364/551.01, 364/580, 364/200, 364/900, 371/15.1, 371/16.5, 371/22.1, 371/22.2, 371/22.4, 371/22.6, 371/23, 371/25.1
• US Class Current: 703/15
• CPC Class Codes: G01R 31/318357 Simulation computer simulation of digital circuits G06F30/3308
• CPC Class Codes: G01R 31/318378 of patterns for devices arranged in a network
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A system and method for selectively simulating logic circuit designs in which a data tables generator receives information from a schematic entry program or netlist entry file and produces data tables for use by a simulator. A designer provides inputs to the data tables generator from a schematic entry program or a netlist entry file. The data tables generator generates from the information received a table of used integrated circuits and a table of their connections. A simulator then receives the output from the data tables generator and produces a design simulation program table that executes integrated circuit model subroutine stored in an integrated circuit model reference library and netlist subroutines stored in a netlist connectivity table. The system may also be used for testing logic circuits on a printed circuit board by capturing signals from a potentially defective logic section of the printed circuit board and feeding them into test points of the integrated circuit simulated by the computer simulator.

Claims

1. A logic circuit design simulation system comprising;

data table generating means for generating incrementally modifiable design elements table and incrementally modifiable connectivity table;

logic circuit design entry means for entering logic circuit design data into said data table generating means;

integrated circuit model input means for entering integrated circuit model data into said data table generating means;

simulating means including;

test vector signal entry means for entering test vectors;

design simulation program generating means for generating an executable design simulation program from said modifiable design elements table, said modifiable connectivity table and selected test vectors entered into said simulating means; and

executing means for executing said design simulation program;

whereby one or more selected values in either or both of said modifiable design elements table and said modifiable connectivity table may be incrementally modified with logic circuit design data for quick simulation of a logic circuit design.

2. The system according to claim 1 in which said logic circuit design entry means comprises either schematic data entry means or netlist connectivity data entry means or both.

3. The system according to claim 2 in which said schematic data entry means includes display means for displaying data being entered for selective entry into said data table generating means.

4. The system according to claim 1 wherein said integrated circuit model input means comprises;

a model reference library; and

a model reference index providing pointers to selected circuit models stored in said model reference library.

5. The system according to claim 1 in which said design elements table includes means for indicating which elements are to be used in a logic design simulation.

6. The system according to claim 5 in which said means for indicating which elements are to be used may be modified by said logic circuit design entry means;

whereby a revised design simulating program may be quickly generated.

7. The system according to claim 1 in which said test vector signal entry means includes a logic analyzer;

said logic analyzer capturing test signals from a logic circuit for entry into said simulating means.

8. The system according to claim 7 in which said logic analyzer is directly connected to a logic circuit on a printed circuit board for capturing and transferring logic circuit data to said simulation system.

9. The system according to claim 1 including test vector editing means for modifying said test vectors before entering said test vectors into said simulating means.

10. A method for simulating selected logic circuit comprising;

entering logic circuit design data;

entering integrated circuit model data;

generating incrementally modifiable design elements table and incrementally modifiable connectivity table from said logic circuit design data and said integrated circuit model data entered;

simulating operation of said selected logic circuit;

said simulation including;

entering test vector signals into simulating means;

generating an executable design simulation program from said design elements table, said connectivity table, and said test vectors; and

executing said executable design simulation program;

whereby one or more selected values in either or both of said modifiable design elements table and said modifiable connectivity table may be incrementally modified with logic circuit design data for quick simulation of a logic circuit design.

11. The system according to claim 10 in which entering said logic circuit design data comprises;

entering either schematic data or netlist connectivity data or both.

12. The system according to claim 11 including displaying said entered data on display means for modification before entry if desired.

13. The system according to claim 10 in which entering integrated circuit model data comprises;

entering referencing data to selectively reference integrated circuit models stored in an integrated circuit model reference library.

14. The system according to claim 10 including generating a used or not-used indication for all elements generated in said modifiable design elements table.

15. The system according to claim 14 including modifying said used indication in said design elements table to select or deselect one or more design elements for simulation.

16. The system according to claim 10 in which entering test vector signal data comprises entering data signals captured from a logic circuit by a logic analyzer.

17. The system according to claim 16 including directly connecting said logic circuit analyzer to a selected logic circuit on a printed circuit board for entry and simulation in said simulator.