EEPROM device including read, write, and erase voltage switching circuits

• US 5,051,953 A
• Filed: 12/18/1989
• Issued: 09/24/1991
• Est. Priority Date: 06/11/1987
• Status: Expired due to Term

• Current Assignee: OKI Electric Industry Company Limited
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Ono, Takashi, Kitazawa, Shooji
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US07/453,073
• Time in Patent Office: 645 Days
• Field of Search: 365/104, 365/184, 365/185, 365/189.09, 365/218, 365/230.06
• US Class Current: 365/185.33
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits

Abstract

An electrically erasable nonvolatile semiconductor device of a high density of integration includes a memory matrix array formed of a plurality of MOS memory transistors. In an erasing operation, a voltage to turn off one selected MOS memory transistor is applied to the control gate electrode of the selected MOS memory transistor. At the same time, a voltage near the breakdown voltage of the selected MOS memory transistor is applied to the first electrode (e.g.--source electrode) of the selected MOS memory transistor and a predetermined voltage is applied to the second electrode (e.g.--drain electrode) of the same MOS memory transistor.

Claims

1. An electrically erasable programmable read only memory device comprising:

(a) a semiconductor substrate;

(b) a memory matrix array formed on said semiconductor substrate, comprising a plurality of MOS memory elements, each having a floating gate, and a plurality of word lines arranged in rows and a plurality of data lines arranged in columns, each of said word lines being associated with a plurality of MOS memory elements, and each of said data lines being associated with a plurality of MOS memory elements, and each of said MOS memory elements having a control gate electrode connected to an associated word line, a first region connected to an associated data line and a second region connected to a third line;

(c) a word line decoder connected to said plurality of word lines for selecting one of said word lines and for applying a first voltage to the control gate electrode of a selected MOS memory element connected to the selected word lines during an erasing operation;

(d) a switching circuit connected to said data lines for providing a second voltage to a selected one of said data lines to generate an avalanche current which flows from a first region of the selected MOS memory element toward said substrate, thus performing an erasing operation by neutralizing electric charges of a floating gate of the selected MOS memory element, said second voltage being slightly smaller than a breakdown voltage of the selected MOS memory element;

(e) a reading and writing circuit connected to said switching circuit for providing said second voltage to said switching circuit; and

(f) a means connected to said third line for providing a third voltage to said second region of said selected MOS memory element which is higher than a substrate voltage generated due to the avalanche current flowing from the first region of said selected MOS memory element toward said substrate so as to suppress a breakdown effect of said selected MOS memory element during an erasing operation.

2. A device according to claim 1, wherein said means for providing said third voltage comprises enhancement MOS transistors, and wherein said third voltage is provided in response to an erasing control signal applied to said enhancement MOS transistors.

3. An electrically erasable programmable read only memory device comprising:

(a) a semiconductor substrate;

(b) a memory matrix array formed on said semiconductor substrate, comprising a plurality of MOS memory elements, each having a floating gate, and a plurality of word lines arranged in rows and a plurality of data lines arranged in columns, and a plurality of third lines, each of said word lines being associated with a plurality of MOS memory elements, and each of said MOS memory elements having a control gate electrode connected to an associated word line, a first region connected to an associated data line and a second region connected to a third line;

(c) a first row decoder connected to said word lines for selecting one of said word lines and for applying a first voltage to the selected word line and to a control gate electrode of a selected MOS memory element associated with the selected word line during an erasing operation;

(d) a switching circuit connected to said data lines for providing a second voltage to a selected data line selected from said data lines and to a first region of said selected MOS memory element associated with the selected data line to generate an avalanche current which flows from the first region of said selected MOS memory element toward said substrate, thus performing an erasing operation by neutralizing electric charges of said floating gate of said selected MOS memory element, said second voltage slightly smaller than a breakdown voltage of said selected MOS memory element;

(e) a reading and writing circuit connected to said switching circuit for providing said second voltage to said switching circuit; and

(f) a second row decoder, connected to said third lines, for selecting one of said third lines and for applying a third voltage thereto in response to an erasing signal, wherein said third voltage is higher than a substrate voltage generated due to an avalanche current flowing from the first region of said selected MOS memory element toward said substrate so as to suppress a breakdown effect during an erasing operation.

4. An electrically erasable programmable read only memory device comprising:

(a) a semiconductor substrate;

(b) a memory matrix array formed on said semiconductor substrate, comprising a plurality of MOS memory elements, each having a floating gate, said MOS memory elements being arranged in rows and columns, word lines and data lines, each of said MOS memory elements having a control gate electrode connected to an associated word line, a first region formed in a portion of said substrate and connected to an associated data line and a second region formed in another portion of said substrate and connected to a third line;

(c) a first means connected to at least one of said word lines for applying a first voltage which prevents the formation of a channel region between said first and second regions of each MOS memory element which is supplied with the first voltage through a word line connected to said first means;

(d) a second means connected to a selected data line which is connected to a first region of a selected MOS memory element selected from said MOS memory elements for providing a second voltage to said selected data line to generate an avalanche current which flows from said first region of said selected MOS memory element toward said substrate, thus performing an erasing operation by neutralizing electric charges of said floating gate of said selected MOS memory element voltage being slightly smaller than a breakdown voltage of said selected MOS memory element; and

(e) a third means connected to a third line connected to a second region of said selected MOS memory element for providing a third voltage to said second region of said selected MOS memory element which is higher than a substrate voltage generated due to the avalanche current flowing from said first region of said selected MOS memory element toward said substrate so as to suppress a breakdown effect during an erasing operation.

5. An electrically erasable programmable read only memory device comprising:

(a) a semiconductor substrate;

(b) a memory matrix array formed on said semiconductor substrate, comprising a plurality of word lines arranged in rows, a plurality of data lines arranged in columns, a plurality of third lines, and a plurality of MOS memory elements, each of said MOS memory elements having a floating gate, a control gate electrode connected to an associated word line, a first region connected to an associated data line and a second region connected to an associated third line;

(c) a first row decoder connected to said word lines for selecting one of said word lines and for supplying a first voltage to the selected word line and to the control gate electrode of a selected MOS memory element selected from said MOS memory elements associated with the selected word line during an erasing operation;

(d) a switching circuit connected to said data lines for providing a second voltage to a selected data line selected from said data lines so as to perform an erasing operation by neutralizing electric charges of a floating gate of the selected MOS memory element connected to the selected data line, said second voltage being slightly smaller than a breakdown voltage of the selected MOS memory element;

(e) a reading and writing circuit connected to said switching circuit for providing said second voltage to said switching circuit; and

(f) a second row decoder connected to said third lines for selecting one of said third lines and for applying a third voltage thereto in response to an erasing signal so that one MOS memory element is selected, wherein said third voltage is higher than a substrate voltage generated due to an avalanche current flowing from the first region of said selected MOS memory element toward said substrate so as to suppress a breakdown effect during an erasing operation.

6. An electrically erasable programmable read only memory device comprising:

(a) a semiconductor substrate;

(b) a MOS memory element formed on said semiconductor substrate, said MOS memory element having a floating gate, a control gate electrode, a first region formed in a part of said substrate, and a second region formed in another part of said substrate;

(c) a first line connected to said control gate electrode of said MOS memory element;

(d) a second line connected to said first region of said MOS memory element;

(e) a third line connected to said second region of said MOS memory element;

(f) a first means connected to said first line for supplying a first voltage to said control gate electrode so as to prevent the formation of a channel region between said first and second regions;

(g) a second means connected to said second line for providing a second voltage to said first region so as to allow an avalanche current to flow between said first region and said substrate and to prevent the flow of a channel current between said first region and second region, thus performing an erasing operation by neutralizing electric changes of said floating gate, wherein said second voltage is slightly smaller than a breakdown voltage of said MOS memory element;

(h) a third means connected to said third line for providing a third voltage to said second region, wherein said third voltage is higher than a substrate voltage generated due to the avalanche current so as to suppress a breakdown effect during an erasing operation.

7. A device according to claim 6, wherein said first voltage, second voltage and third voltage are provided in response to an erasing control signal which is inputted to said first means, second means and third means.