Built-in-test by signature inspection (bitsi)

• US 5,051,996 A
• Filed: 03/27/1989
• Issued: 09/24/1991
• Est. Priority Date: 03/27/1989
• Status: Expired due to Fees

• Current Assignee: United States Of America As Represented By The Department Of Energy
• Original Assignee: United States Department of Energy (Government of the United States of America)
• Inventors: Morneau, Richard A., Bergeson, Gary C.
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): BEAUSOLIEL JR, ROBERT W
• Application Number:
  US07/328,917
• Time in Patent Office: 911 Days
• Field of Search: 371/22.4, 371/22.5, 371/22.1, 371/22.3, 371/22.6, 371/25.1, 371/27, 371/15.1, 324/73.1
• US Class Current: 714/732
• CPC Class Codes: G06F 11/277 with comparison between actual response and known fault-free response

Abstract

A system and method for fault detection for electronic circuits. A stimulus generator sends a signal to the input of the circuit under test. Signature inspection logic compares the resultant signal from test nodes on the circuit to an expected signal. If the signals do not match, the signature inspection logic sends a signal to the control logic for indication of fault detection in the circuit. A data input multiplexer between the test nodes of the circuit under test and the signature inspection logic can provide for identification of the specific node at fault by the signature inspection logic. Control logic responsive to the signature inspection logic conveys information about fault detection for use in determining the condition of the circuit. When used in conjunction with a system test controller, the built-in test by signature inspection system and method can be used to poll a plurality of circuits automatically and continuous for faults and record the results of such polling in the system test controller.

Claims

1. A system for fault detection in a digital circuit having input and test points, said system for fault detection comprising:

control logic means coupled to the circuit under test where said control logic means is capable of controlling the overall test by responding to a signature inspection logic means when said signature inspection logic means detects a fault in the circuit by comparing the response of a test generated signal with an expected signal response,

a stimulus generator coupled to the input of the circuit and said control logic means which is responsive to said control logic means and is capable of sending stimulus vector signals to the input of the circuit where said stimulus generator includes;

a stimulus counter linked to a stimulus test vector memory,

a data input multiplexer means coupled to the test points on the circuit,

signature inspection logic means coupled and responsive to said data input multiplexer, said signature inspection logic means capable of comparing a signal received from said data input multiplexer to an expected signal where said signature inspection logic means includes;

a signature analyzer coupled and responsive to said data input multiplexer means and said stimulus test vector memory, a signature counter coupled and responsive to said control logic means and said stimulus counter, a signature memory coupled and responsive to said signature counter, said signature memory capable of storing expected signals associated with each test point of the circuit, and a signature comparator coupled and responsive to said signature analyzer and said signature memory, said signature comparator capable of sending a signal to said control logic means upon detection of a signal from said signal analyzer that does not match an expected signal from said signature memory,

2. A system for fault detection in a digital circuit having input and test points, said system for fault detection comprising:

a stimulus generator coupled to the input of the circuit under test and capable of sending stimulus vector signals to the input of the circuit,

a data input multiplexer means coupled to the test points on the circuit,

signature inspection logic coupled and responsive to said data input multiplexer, said signature inspection logic capable of comparing a signal received from said data input multiplexer to an expected signal, and

control logic coupled to the circuit, said signature inspection logic and said stimulus generator, said control logic capable of enabling imitation of generation of a stimulus signal from said stimulus generator, and further in which said control logic is capable of signaling detection of fault in the circuit if comparison of a signal by said signature inspection logic does not match with the expected signal, whereby fault can be detected in the circuit;

wherein said stimulus generator includes a stimulus counter coupled and responsive to said control logic and coupled to said signature inspection logic,

a stimulus test vector memory coupled to said stimulus counter, said signature inspection logic and the circuit under test, said stimulus test vector memory capable of storing stimulus vectors corresponding to the input and test points of the circuit under test, and

further wherein said stimulus counter is capable of generating stimulus vector address signals for the input of the stimulus test vector memory;

wherein which said signature inspection logic includes a signature analyzer coupled and responsive to said data input multiplexer means and said stimulus test vector memory,

a signature counter coupled and responsive to said control logic and said stimulus counter,

a signature memory coupled and responsive to said signature counter, said signature memory capable of storing expected signals associated with each test point of the circuit,

a signature comparator coupled and responsive to said signature analyzer and said signature memory, said signature comparator capable of sending a signal to said control logic upon detection of a signal from said signature analyzer that does not match an expected signal from said signature memory;

wherein said data input multiplexer means includes an external data input multiplexer means includes an external data input multiplexer coupled to the test points on the circuit, and

an internal data input multiplexer means coupled to said external data input multiplexer and capable of sending a signal to said signature analyzer.

3. The system of claim 2 in which said signature inspection logic also includes means for determining a fault location and further in which said control logic is capable of conveying a signal that identifies the fault location.

4. The system of claim 3 including a system test controller coupled to said control logic and said signature inspection logic, said system test controller capable of initating fault detection and recording the detection of faults.

5. The system of claim 4 in which said control logic, said stimulus counter, said signature counter, said signature comparator, said signature analyzer, and said internal data input multiplexer are contained on a single application specific integrated microchip.

6. A means for fault detection in a system having a plurality of circuits and in which each circuit has inputs and test nodes, said means for fault detection in a system comprising:

a system test controller coupled to each circuit of the plurality of circuits of the system,

a stimulus generator coupled to the input of each circuit of the plurality of circuits, said stimulus generator capable of sending a stimulus vector signal to the input of each circuit of the plurality of circius where said stimulus generator includes;

a stimulus counter coupled to a stimulus test vector memory where said stimulus counter is capable of addressing the input of said stimulus test vector memory where said stimulus test vector memory is capable of storing stimulus vectors corresponding to the input and test points of each circuit of the plurality of circuits under test,

a data input multiplexer means coupled to the test points on each circuit of the plurality of circuits,

signature inspection logic means coupled and responsive to said data input multiplexer means, said signature inspection logic means capable of comparing a signal received from said data input multiplexer means to an expected signals where said signature inspection logic means includes;

a signature analyzer coupled to and responsive to said data input multiplexer means and said stimulus test vector memory, a signature counter coupled and responsive to a control logic means and said stimulus counter, a signature memory capable of storing expected signals associated with each test point of each circuit of the plurality of circuits, a signature comparator coupled and responsive to said signature analyzer and said signature memory, said signature comparator capable of sending a signal to said control logic upon detection of a signal from said signature analyzer that does not match an expected signal from said signature memory, and

control logic means coupled to each circuit of the plurality of circuits, said signature inspection logic means and said stimulus generator, said control logic means capable of enabling initiation of generation of a stimulus vector signal from said stimulus generator, and further in which said control logic means is capable of signaling detection of fault in each circuit of the plurality of circuits if comparison of a signal by said signature inspection logic does not match with the expected signal, whereby fault can be detected in each circuit of the plurality of circuits.

7. The means for fault detection of claim 6 in which said data input multiplexer means includes:

an external data input multiplexer coupled to the test points on each circuit of the plurality of circuits, and an internal data multiplexer means coupled to said external data input multiplexer and capable of sending a signal to said signature analyzer.

8. The means for fault detection of claim 7 in which said signature inspection logic also includes means for determining a fault location in a circuit and further in which said control logic is capable of conveying a signal that identifies the fault location.

9. The means for fault detection of claim 8 in which said control logic, said stimulus counter, said signature counter, said signature comparator, said signature analyzer, and said internal data input multiplexer means are included on each circuit of the plurality of circuits.

10. The means for fault detection of claim 9 in which each circuit of the plurality of circuits includes a application specific integrated circuit microchip that includes said control logic, said stimulus counter, said signature counter, said signature comparator, said signature analyzer, and said internal data input multiplexer means.

11. In a system for fault detection in a circuit, the system including a circuit havng an input and test points, a stimulus test vector memory containing stimulus vectors for the input of the circuit, and a signature memory containing an expected signature signal for each test point of the circuit, a built-in test by signature inspection module comprising:

control logic,

a stimulus counter coupled and responsive to said control logic, and also coupled to the stimulus test vector memory, said stimulus counter and stimulus test vector memory are capable of generating a stimulus vector signal for the input of the circuit associated with each test point of the circuit,

a data input multiplexer coupled to the test points of the circuit and which includes;

an external data input multiplexer coupled and responsive to the signature counter and the test points of the circuit and in which said data input multiplexer is coupled and responsive to the external data input multiplexer

a signature analyzer coupled and responsive to said data input multiplexer and the stimulus test vector memory,

a signature counter coupled to said control logic and said stimulus counter, said signature counter capable of signaling the signature memory,

a signature comparator coupled and responsive to said signature analyzer and the signature memory, said signature comparator capable of sending a signal to said control logic upon detection of a signal from said signature analyzer that does not match an expected signature signal from the signature memory.

12. The built-in test by signature inspection module of claim 11 in which the module is included on a single application specific integrated microchip.

13. A method for detecting faults in a circuit having a circuit input and test points, the method comprising:

sending a stimulus vector signal to the circuit input from a stimulus generator,

receiving a signal from a test point of the circuit in response to the stimulus signal,

comparing the signal received from the test point to an expected signal associated with that test point stored in a signature memory,

indicating that a fault exists in the circuit if the signal received from the test point does not match the expected signal stored in the signature memory,

stopping the test if the signal received from the test point does not match the expected signal stored in the signature memory,

performing fault diagnosis in the go/no-no mode when the purpose of the test is to accept or reject the entire circuit and where LED indicator lights describes the circuit as good or bad,

performing fault diagnosis in a fault isolation mode when the purpose of the test is to pinpoint the fault'"'"'s location within the circuit,

means for operating said stimulus generator using an active technique where a special test stimulus is generated, and

means for testing said circuit using a passive technique by applying normal system inputs during normal system operation.

14. The method of claim 13 in which the step of sending a stimulus vector signal to the circuit is preceded by:

identifying a set of test nodes on the circuit under test wherein a specific test node identifies with a specific vector signal, and

identifying a predetermined order for examination of the test nodes by a signature analyzer.

15. The method of claim 14 including the step of:

indicating the location of the test point at which a fault exists based on said predetermined order of test node examination and the contents of a signature counter at the time the test was terminated by a control logic means.

16. The method of claim 15 in which fault detection of test points on the circuit proceeds according to a predetermined order from an input side of the circuit to an output side such that the first incorrect signature encountered will pinpoint the location of a fault.