Data block deinterleaving and error correction system

• US 5,051,998 A
• Filed: 06/28/1989
• Issued: 09/24/1991
• Est. Priority Date: 06/28/1988
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Satoh, Isao, Murai, Katsumi, Kuroki, Yuzuru
• Primary Examiner(s): Beausoliel, Robert W.
• Application Number:
  US07/372,585
• Time in Patent Office: 818 Days
• Field of Search: 371/39.1, 371/38.1, 371/40.3, 371/40.1, 371/42, 371/47.1, 371/65, 371/37.5, 371/37.8, 371/2.1, 371/2.2, 371/5.1, 371/5.3, 371/5.4
• US Class Current: 714/762
• CPC Class Codes: G11B 20/1809 by interleaving

Abstract

A deinterleaving and error correction system which is advantageously utilized in a playback system of an optical recording disk apparatus. As each block of sector data, encoded for example with the Reed-Solomon error correction code with block interleaving, is read from the disk, the positions within the data block at which drop-out of the playback signal occurs are respectively stored in a memory in which the data symbols are also stored, with these drop-out positions being stored as error position data. Error correction processing is executed using the error position data in conjunction with the code words, enabling the maximum number of correctable errors for each sector to be substantially increased using a simple system configuration.

Claims

1. In an apparatus for recovering data symbols from an input data signal, including demodulation means for demodulating said input data signal to obtain said data symbols, a system for deinterleaving and error correction of a fixed number of data symbols of a block of data formed as a plurality of interleaved error correction code words, the system comprising:

memory means;

means for storing sets of said symbols produced from said demodulation means as respective code words in an array of addresses of said memory means corresponding to a predetermined error correction code array format;

means for detecting signal quality deterioration conditions of said input data signal which indicate occurrences of error symbols;

means for counting numbers of said error symbols occurring in respective ones of said code words, to obtain respective error symbol count values;

means for storing in said memory means at addresses determined by said error symbol count values, as error position data, respective addresses in said memory means of error symbols which coincide with detection of said signal quality deterioration condition;

means functioning after a final one of said fixed number of data symbols has been obtained from said demodulation means for writing final ones of said error symbol count values into predetermined addresses of said memory means; and

error correction means functioning after said final error symbol count values have been written int he memory means for operating on said data symbols, error position data, and error symbol count values, to execute error correction processing.

2. In an apparatus for recovering data symbols from an input data signal, including demodulation means for demodulating said input data signal to obtain said data symbols, a system for interleaving and error correction of a fixed number of data symbols of a block of data formed as a plurality of interleaved error correction code words, the system comprising:

memory means;

means for storing sets of said symbols produced from said demodulation means as respective code words in an array of addresses of said memory means corresponding to a predetermined error correction code array format;

means for detecting signal quality deterioration conditions of said input data signal which indicate occurrences of error symbols;

means for counting respective total members of said error symbols, to obtain symbol count values for respective ones of said code words;

means for generating numeric values representing successive Galois field elements, in response to successive ones of said symbols obtained from said demodulation means;

means for storing in said memory means at addresses determined by said error symbol count values, as error position data, respective ones of said Galois field elements which are generated in coincidence with detection of said signal quality deterioration condition;

means functioning after a final one of said fixed number of data symbols has been supplied, for writing final ones of said error symbol count values into predetermined addresses of said memory means; and

error correction means functioning after said final error symbol count values have been written in the memory means for operating on said data symbols, error position data, and error symbol count values, to execute error correction processing.

3. In an apparatus for recovering data symbols from an input data signal, including means for deriving a recovered clock signal from said input data signal and demodulation means utilizing said recovered clock signal for demodulating said input data signal to obtain said data symbols, a system for deinterleaving and error correction of data symbols of a block of data formed as a plurality of interleaved error correction code words, said block being divided into a plurality of successive frames each comprising an identical number of data symbols, each of the frames being preceded by a fixed-duration resynchronizing signal, the system comprising:

memory means;

detection means responsive to each of said resynchronizing signals for generating a corresponding resynchronizing detection signal;

means for storing sets of said symbols produced from said demodulation means as respective code words in an array of addresses of said memory means corresponding to a predetermined error correction code array format;

means for detecting a signal quality deterioration condition of said input data signal which indicates occurrence of a symbol error and for producing a dropout pulse in synchronism with each of said data symbols which coincides with said condition;

reversible counter means for counting successive ones of said drop-out pulses to produce respective error symbol count values corresponding to said code words;

means responsive to generation of a predetermined number of said drop-out pulses during an n ^th one of said frames for generating a signal indicating that a bit slip condition has possibly occurred within said n^th frame, at a specific position within the frame, and for designating all symbols of said n^th frame which are obtained subsequent to said specific position as being error symbols;

means for storing in said memory means at addresses determined by said error symbol count values, as error position data, respective addresses in said memory means of said error symbols;

means for detecting an actual occurrence of bit slip during a frame by counting a number of periods of said recovered clock signal which occur between two resynchronization signals which respectively immediately precede and immediately succeed said frame;

means functioning, if said actual occurrence of bit slip is not detected for said n^th frame, to execute down-counting by said reversible counter means during an (n+1)^th frame immediately succeeding said n^th frame, by an amount which is identical to a number of error symbols counted as having occurred due to bit slip during said n^th frame;

means functioning after a final one of said fixed number of data symbols has been supplied, for writing final ones of said error symbol count values into predetermined addresses of said memory means; and

error correction means functioning after said final error symbol count values have been written in the memory means for operating on said data symbols, error position data, and error symbol count values, to execute error correction processing.

4. In an apparatus for recovering data symbols from an input data signal including demodulation means for demodulating said input data signal to obtain said data symbols, a system for deinterleaving and error correction of data symbols of a block of data formed as a plurality of interleaved error correction code words, the system comprising:

memory means;

first counter means for counting successive ones of said data symbols to produce, for each of said data symbols, a corresponding symbol count value representing a corresponding one of the code words and a position of said each data symbol within the corresponding code word, and means for writing said each data symbol into said memory means at an address of said memory means that is determined by said symbol count value;

means for detecting a signal quality deterioration condition of said input data signal which indicates occurrence of a symbol error and for producing a drop-out pulse in synchronism with each of said data symbols which coincides with said condition;

second counter means comprising a set of counters respectively corresponding to said code words, controlled by said symbol count value from said first counter means for counting successive ones of said drop-out pulses to produce respective error symbol count values corresponding to said code words, and means for writing into said memory means, in response to each of said drop-out pulses, the corresponding symbol count value from the first counter means as an error position value, said corresponding symbol count value being written into an address of said memory means that is determined by a corresponding one of said error symbol count values;

means functioning after a final one of said fixed number of data symbols has been supplied, for writing final ones of said error symbol count values into predetermined addresses of said memory means; and

error correction means, functioning after said final error symbol count values have been written in the memory means, for operating on said data symbols, said error position values and said error symbol count values to execute error correction processing.

5. In an apparatus for recovering data symbols from an input data signal, including demodulation means for demodulating said input data signal to obtain said data symbols, a system for deinterleaving and error correction of data symbols of a block of data formed as a plurality of interleaved error correction code words, the system comprising:

memory means;

first counter means for counting successive ones of said data symbols to produce, for each of said data symbols, a corresponding symbol count value representing a corresponding one of the code words and a position of said each data symbol within the corresponding code word, and means for writing said each data symbol into said memory means at an address of said memory means that is determined by said symbol count value;

means for detecting a signal quality deterioration condition of said input data signal which indicates occurrence of a symbol error and for producing a drop-out pulse in synchronism with each of said data symbols which coincides with said condition;

second counter means comprising a set of counters respectively corresponding to said code words, controlled by by said symbol count value from said first counter means for counting successive ones of said drop-out pulses to produce respective error symbol count values corresponding to said code words;

third counter means comprising a linear feedback counter responsive to successive ones of said data symbols for multiplying a count value held therein by a fixed amount, to obtain count values expressing respective positions within a Galois field index region of said data symbols which coincide with said signal quality deterioration condition, and means for writing into said memory means, in response to each of said drop-out pulses, a corresponding count value from the third counter means as an error position value, said corresponding count value being written into an address of said memory means that is determined by a correcpoding one of said error symbol count values;

means functioning after a final one of said fixed number of data symbols has been supplied, for writing final ones of said error symbol count values into predetermined addresses of said memory means; and

error correction means, functioning after said final error symbol count values have been written in the memory means, for operating on said data symbols, said error position values and said error symbol count values to execute error correction processing.

6. An apparatus according to claim 5, in which said data block comprises parity data for error correction purposes, and further comprising error correction means for executing error correction based on said parity data, and in which said error correction is executed after all of the symbols of said data block have been stored in said memory means and in which operation of said bit slip processing control means is initiated only if it is found that irrecoverable errors remain after executing said error correcting processing based on the parity data.

7. In an apparatus for recovering data symbols from an input data signal, including means for deriving a recovered clock signal from said input data signal and demodulation means utilizing said recovered clock signal for demodulating said input data signal to obtain said data symbols, a system for deinterleaving and error correction of data symbols of a block of data formed as a plurality of interleaved error correction code words, said block being divided into a plurality of successive frames each comprising an identical number of data symbols, said frames being respectively preceded by fixed-duration resynchronizing signals, the system comprising:

resynchronizing detection means responsive to said resynchronizing signals for generating corresponding resynchronizing detection signals;

resynchronizing prediction means responsive to each of said resynchronizing detection signals for deriving a time of subsequent occurrence of a predicted resynchronizing signal, based on a number of pulses of said recovered clock signal produced during a frame which succeeds said each resynchronizing detection signal;

first comparison means for comparing respective time-axis positions of each of said resynchronizing detection signals and a corresponding predicted resynchronizing signal, and for producing an indication signal if said time-axis positions differ by less than a predetermined amount;

memory means;

first counter means for counting successive ones of said data symbols to produce, for each of said data symbols, a corresponding symbol count value representing a corresponding one of the code words and a position of said each data symbol within the corresponding code word, and means for writing said each data symbol into said memory means at an address of said memory means that is determined by said symbol count value;

means for detecting a signal quality deterioration condition of said input data signal which indicates occurrence of a symbol error and for producing a drop-out pulse in synchronism with each of said data symbols which coincides with said condition;

second counter means comprising a set of reversible counters respectively corresponding to said code words, controlled by said symbol count value from said first counter means for counting successive ones of said drop-out pulses to produce respective error symbol count values corresponding to said code words, and means for writing into said memory means, in response to each of said drop out pulses, a corresponding symbol count value from said second counter means as an error position value, said corresponding symbol count value being written into an address of said memory means that is determined by a corresponding one of said error symbol count values;

third counter means for counting successive ones of said drop-out pulses during each of said frames, beginning from a fixed initial count value at the start of each frame;

means for detecting when a count value in said third counter means exceeds a predetermined error count value, and producing an output signal in response to said detection;

first latch means responsive to said output signal from the count value detection means for producing an output signal which continues until the end of a frame in which said error count value was exceeded;

control means responsive to said first latch means output signal for incrementing said second counter means in response to successive ones of said data symbols;

second latch means for storing a symbol count value from said first counter means corresponding to a symbol position at which said error count value was exceeded;

second comparison means functioning during a frame immediately succeeding said frame in which the error count value was exceeded, for detecting when an error count value of said first counter means coincides with said symbol count value held in said second latch means;

control means responsive to said indication signal from said first comparison means, when coincidence is detected by said second comparison means, for decrementing said second counter means in response to successive ones of said data symbols until the end of said immediately succeeding frame;

means functioning after a final data symbol of said block has been supplied, for writing final ones of said error symbol count values into predetermined addresses of said memory means; and

error correction means, functioning after said final error symbol count values have been written in the memory means, for operating on said data symbols, said error position values and said error symbol count values to execute error correction processing.

8. An apparatus for executing demodulation and error correction of a data block supplied as a serial input data signal, the data signal having a format comprising successive frames each comprising a fixed number of data symbols, each frame being preceded by a clock signal resynchronizing signal, the apparatus comprising:

clock signal recovery means for deriving a recovered clock signal from said data signal;

demodulation means responsive to said recovered clock signal for demodulating said data signal to recover successive ones of said data symbols;

memory means for storing said data symbols;

detection means for detecting successive ones of said resynchronizing signals and for generating a resynchronizing detection signal in response to each resynchronizing signal;

means functioning during each frame of said data signal for counting a number of periods of said recovered clock signal which occur during said each frame, to generate a predicted resynchronizing signal during a final part of said each frame, said predicted resynchronizing signal coinciding with a resynchronization detection signal produced at the start of an immediately succeeding frame, during normal functioning of said clock signal recovery means;

means for detecting a signal quality deterioration condition of said data signal, and for generating error position data indicating positions of respective ones of said data symbols which coincide with occurrences of said signal quality deterioration condition, and for storing said error position data in said memory means;

means for deriving resynchronizing signal status data representing an amount and direction of phase difference between the predicted resynchronizing signal of said each frame and the resynchronization detection signal of said immediately succeeding frame, and for storing said resynchronizing signal status data in said memory means; and

bit slip processing control means functioning after all of the data symbols and resynchronizing status data for said data block have been stored in said memory means, for reading out said resynchronizing status data to determined whether a bit slip condition has occurred within any of said frames, and, for a frame in which bit slip has occurred, successively;

(a) determining a position within the frame at which the bit slip has occurred, based on said signal quality deterioration data for the frame;

(b) reading out from said memory means a portion of the data of the frame, extending from said position at which bit slip occurred up to the end of the frame;

(c) executing an amount of phase shift of said data portion, in a direction and amount such as to compensate for an amount of bit slip indicated by said resynchronizing status data;

(d) modulating said portion for conversion back to a form in which data are expressed in said data signal;

(e) demodulating said portion to obtain successive data symbols; and

(f) storing said symbols in said memory means to replace said data portion of the frame.

9. In an apparatus for recovering data symbols from an input data signal, including means for deriving a recovered clock signal from said input data signal and demodulation means utilizing said recovered clock signal for demodulating said input data signal to obtain said data symbols, a system for deinterleaving and error correction of data symbols of a block of data formed as a plurality of interleaved error correction code words, said block being divided into a plurality of successive frames each comprising an identical number of data symbols, the frames being respectively preceded by fixed-duration resynchronizing signals, the system comprising:

resynchronizing detection means responsive to said resynchronizing signals for generating corresponding resynchronizing detection signals;

resynchronizing prediction means responsive to each of said resynchronizing detection signals for deriving a time of subsequent occurrence of a predicted resynchronizing signal, based on a number of pulses of said recovered clock signal produced during a frame which succeeds said each resynchronizing detection signal;

first comparison means for comparing respective time-axis positions of each of said resynchronizing detection signals and a corresponding predicted resynchronizing signal, and for producing an indication signal if said time-axis positions differ by less than a predetermined amount;

memory means;

first counter means for counting successive ones of said data symbols to produce, for each of said data symbols, a corresponding symbol count value representing a corresponding one of the code words and a position of said each data symbol within the corresponding code word, and means for writing said each data symbol into said memory means at an address of said memory means that is determined by said symbol count value;

means for detecting a signal quality deterioration condition of said input data signal which indicates occurrence of a symbol error and for producing a drop-out pulse in synchronism with each of said data symbols which coincides with said condition;

second counter means comprising a set of reversible counters respectively corresponding to said code words, controlled by said symbol count value from said first counter means for counting successive ones of said drop-out pulses to produce respective error symbol count values corresponding to said code words;

third counter means comprising a linear feedback counter responsive to successive ones of said data symbols for multiplying a count value held therein by a fixed amount, to obtain count values expressing respective positions within a Galois field index region of said data symbols which coincide with said signal quality deterioration condition, and means for writing into said memory means, in response to each of said drop-out pulses, a corresponding count value from the third counter means as an error position value, said corresponding count value being written into an address of said memory means that is determined by a corresponding one of said error symbol count values;

fourth counter means for counting successive ones of said drop-out pulses during each of said frames, beginning from a fixed initial count value at the start of each frame;

means for detecting when a count value in said fourth counter means exceeds a predetermined error count value, and producing an output signal in response to said detection;

first latch means responsive to said output signal from the count value detection means for producing an output signal which continues until the end of a frame in which said error count value was exceeded;

control means responsive to said first latch means output signal for incrementing said second counter means in response to successive ones of said data symbols;

second latch means for storing a symbol count value from said first counter means corresponding to a symbol position at which said error count value was exceeded;

second comparison means functioning during a frame immediately succeeding said frame in which the error count value was exceeded, for detecting when an error count value of said first counter means coincides with said symbol count value held in said second latch means;

control means responsive to said indication signal from said first comparison means, when coincidence is detected by said second comparison means, for decrementing said second counter means in response to successive ones of said data symbols until the end of said immediately succeeding frame;

means functioning after a final data symbol of said block has been supplied, for writing final ones of said error symbol count values into predetermined addresses of said memory means; and

error correction means, functioning after said final error symbol count values have been written in the memory means, for operating on said data symbols, said error position values and said error symbol count values, to execute error correction processing.