Synchronous digital signal to asynchronous digital signal desynchronizer
First Claim
1. Apparatus for desynchronizing an incoming digital signal at an incoming digital clock rate to obtain an outgoing digital signal at an outgoing digital clock rate different from the incoming digital clock rate, the apparatus comprising:
- a source of an incoming digital signal;
a source of an incoming clock signal and incoming frame sync signal;
means for detecting occurrences of pointer adjustments in said incoming digital signal and for generating a first control signal representative of the occurrence and direction of said pointer adjustments, each of said pointer adjustments including a predetermined number of bits;
means for obtaining a gapped data signal from said incoming digital signal;
means for obtaining a gapped clock signal from said incoming clock signal;
means supplied with said frame sync signal and being responsive to said first control signal for adaptively generating an estimate of an interval between said bits in said pointer adjustment and for generating a second control signal at said estimated interval;
means responsive to said first and second control signals for generating a third control signal indicative of a bit adjustment;
a digital phase lock loop for generating an output clock signal, said digital phase lock loop being responsive to a phase adjustment signal;
means for comparing said third control signal and a write address for obtaining said phase adjustment signal; and
elastic store means supplied with said gapped data signal, said gapped clock signal and said output clock signal for supplying as an output a smooth data signal synchronized to said output clock signal, said elastic store including means responsive to said gapped clock signal for generating said write address.
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Accused Products
Abstract
Improved jitter performance is realized in a desynchronizer for obtaining an asynchronous digital signal, e.g., a DS3 signal, from a received synchronous digital signal, e.g., a SONET STS-1 signal. The improved jitter performance results from the use of a unique adaptive bit leaking arrangement in conjunction with a digital phase locked loop and synchronizing elastic store. An estimate of a bit leaking interval is adaptively obtained based on the intervals between a sequence of consecutive pointer adjustments in the received signal, i.e., the STS-1 signal. In one embodiment, the bit leaking interval estimate is obtained by employing a moving average of the intervals between the pointer adjustments. The desired bit leaking is effected by employing an accumulator which is responsive to the received pointer adjustments and a representation of the estimated bit leaking interval, in conjunction with a comparator. The accumulator output count is supplied to the comparator along with the current write address of the elastic store. Leak bits are supplied as an output from the comparator one at a time to the phase locked loop which, in turn, generates a smooth read clock for the elastic store.
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Citations
12 Claims
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1. Apparatus for desynchronizing an incoming digital signal at an incoming digital clock rate to obtain an outgoing digital signal at an outgoing digital clock rate different from the incoming digital clock rate, the apparatus comprising:
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a source of an incoming digital signal; a source of an incoming clock signal and incoming frame sync signal; means for detecting occurrences of pointer adjustments in said incoming digital signal and for generating a first control signal representative of the occurrence and direction of said pointer adjustments, each of said pointer adjustments including a predetermined number of bits; means for obtaining a gapped data signal from said incoming digital signal; means for obtaining a gapped clock signal from said incoming clock signal; means supplied with said frame sync signal and being responsive to said first control signal for adaptively generating an estimate of an interval between said bits in said pointer adjustment and for generating a second control signal at said estimated interval; means responsive to said first and second control signals for generating a third control signal indicative of a bit adjustment; a digital phase lock loop for generating an output clock signal, said digital phase lock loop being responsive to a phase adjustment signal; means for comparing said third control signal and a write address for obtaining said phase adjustment signal; and elastic store means supplied with said gapped data signal, said gapped clock signal and said output clock signal for supplying as an output a smooth data signal synchronized to said output clock signal, said elastic store including means responsive to said gapped clock signal for generating said write address. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification
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- Resources
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Current AssigneeAmerican Telephone & Telegraph Company (AT&T, Inc.)
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Original AssigneeAT&T, Inc.
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InventorsMediavilla, Ricardo, Lane, Donald A., Duff, Donald G.
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Primary Examiner(s)Safourek, Benedict V.
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Application NumberUS07/572,740Time in Patent Office396 DaysField of Search370/48, 370/49, 370/105.3, 370/108, 375/106, 375/117, 375/118, 375/119, 328/55, 328/155, 377/66, 377/78, 365/78, 365/221, 369/60, 307/590, 307/597US Class Current375/262CPC Class CodesH04J 3/076 Bit and byte stuffing, e.g....H04L 5/24 with start-stop synchronous...Y10S 370/907 Synchronous optical network...
