Test device and method for testing electronic device and semiconductor device having the test device

• US 5,053,698 A
• Filed: 10/19/1989
• Issued: 10/01/1991
• Est. Priority Date: 10/28/1988
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Ueda, Koichiro
• Primary Examiner(s): Karlsen, Ernest F.
• Application Number:
  US07/424,042
• Time in Patent Office: 712 Days
• Field of Search: 324/158 R, 324/73.1, 371/25.1, 371/22.3, 371/22.5, 371/22.6, 371/21.2, 371/21.4, 365/201
• US Class Current: 714/736
• CPC Class Codes: G01R 31/31937 Timing aspects, e.g. measuring propagation delay G01R31/3191 and G01R31/31922 take precedence; marginal testing G06F11/24

Abstract

A test device for an electronic device includes a pattern generating circuit, a plurality of comparators and a memory. The pattern generating circuit generates at least one input pattern. The electronic device under test is supplied with the input pattern and generating a corresponding ouput signal. The comparators are connected to the electronic device under test and are supplied with the output signal therefrom. The comparators compare the output signal with an expected output signal with mutually different timing of comparison. The memory stores the comparison results supplied from the comparators. Characteristics of the electronic device under test are obtained from the comparison results stored in the memory.

Claims

1. A test device for an electronic device, comprising:

pattern generating means for generating at least one input pattern, said electronic device under test supplied with said input pattern and said electronic device under test generating a corresponding output signal;

a plurality of comparators in parallel connected to said electronic device under test and supplied with said output signal therefrom, said plurality of comparators comparing said output signal with an expected output signal at mutually different timings of comparison; and

memory means for storing comparison results supplied from said plurality of comparators,

wherein characteristics of said electronic device under test obtained from comparison results stored in said memory means.

2. A test device as claimed in claim 1, further comprising means for generating a strobe signal, and delay means for delaying said strobe signal and generating a plurality of delayed strobe signals which are supplied to said respective comparators, wherein said comparators compares said output signal with said expected value when the corresponding one of said strobe signals is supplied.

3. A test device as claimed in claim 2, wherein said delay means includes a plurality of delay circuits which are connected in series, and said strobe signal generated by said means is applied to the delay circuit of the first stage.

4. A test device as claimed in claim 2, wherein said delay means includes a plurality of delay lines coupled to said respective comparators, and each of said plurality of delay lines includes a specific different number of delay circuits having the same delay time.

5. A test device as claimed in claim 3, wherein each of said delay circuits includes a delay element, and a switch connected to said delay element and drawing the delayed strobe signal supplied therefrom.

6. A test device as claimed in claim 1, further comprising level comparator means, coupled between said electronic device under test and said plurality of comparators, for comparing a level of said output signal supplied from said electronic device under test with predetermined levels and for determining whether said output signal from said electronic device is at a high level or a low level.

7. A test device as claimed in claim 6, wherein said level comparator means includes a first comparator comparing said output signal supplied from said electronic device under test with a high-level reference voltage and outputting a first voltage indicative of a comparison result, and a second comparator comparing said output signal supplied from said electronic device under test with a low-level reference voltage and outputting a second voltage indicative of a comparison result, and wherein said first and second voltages are supplied, as said output signal from said electronic device under test, to said plurality of comparators.

8. A test device as claimed in claim 7, wherein each of said plurality of comparators compares the level of said output signal defined by said first and second voltages with the expected output signal.

9. A test device as claimed in claim 2, wherein said electronic device under test is coupled to said plurality of comparators through a signal line, and wherein said delay time of each of said delayed strobe signals includes a propagation delay time caused by said signal line.

10. A test device as claimed in claim 1, wherein said pattern generating means generates a plurality of different input patterns, and said memory means has a storage capacity which enables said memory means it to be possible to store the comparison results for said different input patterns.

11. A test device as claimed in claim 10, wherein said memory means includes a memory having said storage capacity, and said electronic device under test is a memory device, and wherein said test device further comprises address generating means for generating an address signal to be supplied to said memory and said electronic device under test, and said input patterns correspond to values of said address signal derived from said address generating means.

12. A test device as claimed in claim 11, wherein said memory means and said device under test are supplied with a same address signal derived from said address generating means.

13. A method of testing an electronic device comprising the steps of:

supplying said electronic device under test with at least one input pattern, said electronic device under test generating a corresponding output signal;

comparing said output signal with an expected output signal for a plural number of times at mutually different timings of comparison;

storing the comparison results supplied with different timing in a memory and

obtaining characteristics of said electronic device under test obtaining from the comparison results stored in said memory.

14. A semiconductor device comprising:

a semiconductor chip; and

a test device testing an electronic device, said test device including

pattern generating means for generating at least one input pattern, said electronic device under test supplied with said at least one input pattern and generating a corresponding output signal,

a plurality of comparators in parallel connected to said electronic device under test and supplied with said output signal therefrom, said plurality of comparators comparing said output signal with an expected output signal at mutually different timings of comparison, and

memory means for storing comparison results supplied from said plurality of comparators,

wherein characteristics of said electronic device under test obtained from comparison results stored in said memory means.