Semiconductor nonvolatile memory

• US 5,053,842 A
• Filed: 05/30/1990
• Issued: 10/01/1991
• Est. Priority Date: 05/30/1990
• Status: Expired due to Term

• Current Assignee: Seiko Instruments Incorporated (Seiko Group)
• Original Assignee: Seiko Instruments Incorporated (Seiko Group)
• Inventors: Kojima, Yoshikazu
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): Hung, Dang Xuan
• Application Number:
  US07/530,269
• Time in Patent Office: 489 Days
• Field of Search: 357/23.5, 357/55, 357/54, 357/23.5, 365/185
• US Class Current: 257/316
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The invention is directed to a semiconductor nonvolatile memory of the floating gate type having dual gate structure comprised of a first channel region having a channel resistance controlled by a control gate electrode and a second channel region having a channel resistance controlled by a floating gate electrode. The first channel region is formed on one face section of semiconductor substrate which has a crystal face orientation different from that of another face section on which the second channel region is formed. By such construction, channel length of the first and second channel regions can be shortened to increase memory capacity density and to improve quality.

Claims

1. A semiconductor nonvolatile memory comprising:

a semiconductor substrate of a first conductivity type having a stepped portion having a top face section and a bottom face section separated from one another by a side face section;

a source region of a second conductivity type provided in the top face section of the stepped portion;

a drain region of the second conductivity type provided in the bottom face section of the stepped portion;

a first channel region adjacent to the source region and formed in the side face section and in a part of the bottom face section of the stepped portion;

a second channel region formed between the first channel region and the drain region in the bottom face section of the stepped portion;

a control gate electrode formed over the first channel region and the source region through a gate insulating film for controlling the first channel region conductance; and

a floating gate electrode formed over the second channel region through a gate insulating film for controlling the second channel region conductance.

2. A semiconductor nonvolatile memory according to claim 1;

wherein the top and bottom face sections are parallel to one another.

3. A semiconductor nonvolatile memory according to claim 1;

wherein the side face section extends at given angles relative to the top and bottom face sections.

4. A semiconductor nonvolatile memory according to claim 3;

wherein the given angle between the top and side face sections is approximately 90°

.

5. A semiconductor nonvolatile memory according to claim 3;

wherein the given angle between the bottom and side face sections is approximately 90°

.

6. A semiconductor nonvolatile memory according to claim 1;

wherein the control gate electrode and floating gate electrode are disposed in side-by-side relation and are separated from one another by a gate insulating film.

7. A semiconductor nonvolatile memory according to claim 1;

wherein the first and second channel regions each have a length having an accuracy on the order of about 100 Å

.

8. A semiconductor nonvolatile memory according to claim 1;

wherein the source and drain regions are of the N⁺ type; and

further including an additional drain region of the N^- type interposed between the N⁺ type drain region and the bottom face section of the stepped portion.

9. A semiconductor nonvolatile memory comprising:

a semiconductor substrate of a first conductivity type having a stepped portion having a top face section and a bottom face section separated from one another by a side face section;

a source region of a second conductivity type provided in the bottom face section of the stepped portion;

a drain region of the second conductivity type provided in the top face section of the stepped portion;

a first channel region adjacent to the source region and formed in the bottom face section of the stepped portion;

a second channel region formed between the drain region and the first channel region in the side face section and in a part of the bottom face section of the stepped portion;

a control gate electrode formed over the first channel region and the source region through a gate insulating film for controlling the first channel region conductance; and

a floating gate electrode formed over the second channel region through a gate insulating film for controlling the second channel region conductance.

10. A semiconductor nonvolatile memory according to claim 9;

wherein the top and bottom face sections are parallel to one another.

11. A semiconductor nonvolatile memory according to claim 9;

wherein the side face section extends at give angles relative to the top and bottom face sections.

12. A semiconductor nonvolatile memory according to claim 11;

wherein the given angle between the top and side face sections is approximately 90°

.

13. A semiconductor nonvolatile memory according to claim 11;

wherein the given angle between the bottom and side face sections is approximately 90°

.

14. A semiconductor nonvolatile memory according to claim 9;

wherein the control gate electrode and floating gate electrode are disposed in side-by-side relation and are separated from one another by a gate insulating film.

15. A semiconductor nonvolatile memory according to claim 9;

wherein the first and second channel regions each have a length having an accuracy on the order of about 100 Å

.

16. A semiconductor nonvolatile memory according to claim 9;

wherein the source and drain regions are of the N⁺ type; and

further including an additional drain region of the N^- type interposed between the N⁺ type drain region and the top face section of the stepped portion.