Apparatus for aligning arithmetic operands during fetch

• US 5,053,953 A
• Filed: 01/05/1990
• Issued: 10/01/1991
• Est. Priority Date: 01/05/1990
• Status: Expired due to Fees

• Current Assignee: Bull HN Information Systems Incorporated (Atos SE)
• Original Assignee: Bull HN Information Systems Incorporated (Atos SE)
• Inventors: Patel, Shirish
• Primary Examiner(s): Fleming, Michael R.
• Assistant Examiner(s): Auve, Glenn A.
• Application Number:
  US07/461,554
• Time in Patent Office: 634 Days
• Field of Search: 364/200, 364/900
• US Class Current: 712/300
• CPC Class Codes: G06F 5/01 for shifting, e.g. justifying, scaling, normalising digital stores in which the information is moved stepwise, e.g. shift-registers G11C19/00; digital stores in which the information circulates G11C21/00
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30192 according to data descriptor, e.g. dynamic data typing
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing

Abstract

In a digital computer system in which arithmetic operands are addressed in instructions by their most significant digits, and in which operands need not start or end on particulr boundaries in system memory, apparatus is provided for calculating information from data available during instruction decoding and for using that information during operand fetching to fetch operands least significant digit first, and to store them in a scratchpad memory right-justified on double-word boundaries and filled with leading zeros.

Claims

1. In a data processing system having a memory for storing instructions and operands, and having means for sequentially retrieving the instructions and having means responsive to the instructions for performing operations upon the operands,

the memory being organized as contiguous addressable words, each word comprising an integral multiple of eight bits, the memory being adapted to retrieve and store double words each comprising two contiguous words beginning on an even-numbered word address called a double word boundary,

the operands being stored in the memory as contiguous packed (four-bit binary coded decimal (BCD)) digits which may begin and end on any four-bit boundary within a word, an operand'"'"'s most significant digit being its leftmost or lowest-addressed digit,

the instructions having provision to specify each operand'"'"'s length, its type as packed, the memory double word address in which it begins, and its offset in digits from its double-word boundary to its first digit,

said means for performing operations upon the operands including an arithmetic processor including a scratchpad memory organized as contiguous double words for receiving and holding operands retrieved from the memory and ALU means connected to the scratchpad memory for performing arithmetic operations upon the operands,

alignment apparatus for presenting retrieved operands to the scratchpad memory right-justified on double word boundaries, comprising:

first means coupled to said memory for receiving each instruction, said first means for calculating from said length, type and offset provided in the instruction, a number of double words that must be fetched from the memory in order to retrieve the entire operand, the number being designated NDWF;

second means operatively coupled to said first means and to said memory for receiving said each instruction, said second means for calculating from said length, type and offset provided in the instruction, a number of digit positions the operand must be shifted to the right in order to right-justify it on a double-word boundary, the number being designated RSFT;

third means operatively coupled to said first means and to said memory for receiving said each instruction, said third means (316, 350, 354, 368,

     370) for calculating from said length and type provided in the instruction, a number of zeros required to precede the operand in a scratchpad memory double word, the number being designated RLZR;

fourth means operatively coupled to said first means, second means and to said memory, said fourth means for fetching from the memory, NDWF double words containing the operand, starting with the operand'"'"'s highest addressed word and progressing consecutively through lower addresses;

first and second register means coupled to said memory, said first register means for holding a double word most recently fetched from the memory and second register means for holding a double word next most recently fetched from the memory;

fifth means coupled to said first and second register means and to said scratchpad memory, said fifth means selecting from the first and second register means, a number of said first register'"'"'s rightmost digits, the number being equal to RSFT, and a number of said second register'"'"'s leftmost digits, the number being equal to the difference between the number of digits in a double word and RSFT, and said fifth means storing in a double word location in the scratchpad memory a double word having as its leftmost digits the digits selected from the most recently fetched double word and as its rightmost digits the digits selected from the next most recently fetched double word; and

sixth means coupled to said memory and to said fifth means, said sixth means responsive to a completion of fetching NDWF double words from the memory for inserting in the double word to be stored in the scratchpad memory RLZR leading zero digits so that the operand is stored in the scratchpad memory right justified on a double word boundary and filled with leading zeros staring from a double word boundary.

2. The data processing system recited in claim 1, wherein further:

the operands may alternatively be stored in the memory as contiguous zoned (eight-bit ASCII or EBCDIC coded numbers) which may begin and end on any eight-bit boundary within a word,

the instructions have provision for specifying the type of each operand as packed or zoned, and wherein said alignment apparatus further includes seventh means connected to the input of the first register means and responsive to a zoned type specification for selecting four least significant bits of every eight-bit ASCII or EBCDIC byte received in the double word retrieved from the memory and transferring said four least significant bits to the first register means as a BCD digit.

3. The data processing system recited in claim 2, wherein further:

the operands may further include leading signs or trailing signs;

the instructions have provision for specifying each operand'"'"'s type as one of packed unsigned, packed with trailing sign, zoned unsigned, zoned with leading sign, or zoned with trailing sign.

4. A method of aligning operands retrieved from a memory for storing instructions and operands of a system which includes means for sequentially retrieving the instructions and has means responsive to the instructions for performing operations upon the operands, said memory being organized as contiguous addressable words, each word comprising an integral multiple of eight bits, the memory being adapted to retrieve and store double words each comprising two contiguous words beginning on an even-numbered word address called a double word boundary, the operands being stored in the memory as contiguous packed (four-bit binary coded decimal (BCD)) digits which may begin and end on any four-bit boundary within a word, an operand'"'"'s most significant digit being its leftmost or lowest-addressed digit, the instructions having provision to specify each operand'"'"'s length, its type as packed, the memory double word address in which it begins, and its offset in digits from its double-word boundary to its first digit, said means for performing operations upon the operands including an arithmetic processor including a scratchpad memory organized as contiguous double words for receiving and holding operands retrieved from the memory and ALU means connected to the scratchpad memory for performing arithmetic operations upon the operands, said method of aligning retrieved operands for presentation to the scratchpad memory right-justified on double word boundaries comprising the steps of:

first calculating from said length, type and offset provided in the instruction a number of double words that must be fetched from the memory in order to retrieve the entire operand, the number being designated NDWF;

next calculating from said length, type and offset provided in the instruction, a number of digit positions the operand must be shifted to the right in order to right-justify it on a double-word boundary, the number being designated RSFT;

then calculating from said length and type provided in the instruction a number of zeros required to precede the operand in a scratchpad memory double word, the number being designated RLZR;

fetching from the memory, NDWF double words containing the operand, starting with the operand'"'"'s highest addressed double word and progressing consecutively through lower addresses;

storing a double word most recently fetched from the memory and a double word most recently fetched from the memory in first and second registers respectively;

selecting from the first and second registers, a number of said first registers rightmost digits, the number being equal to RSFT, and a number of said second register'"'"'s leftmost digits, the number being equal to the difference between the number of digits in a double word and RSFT;

storing in a double word location in the scratchpad memory a double word having as its leftmost digits the digits selected from the most recently fetched double word and as its rightmost digits the digits selected from the next most recently fetched double word; and

,

inserting in the double word to be stored in the scratchpad memory RLZR leading zero digits upon completion of fetching NDWF double words from memory so that the operand is stored in the scratchpad memory right justified on a double word boundary and filled with leading zeros starting from a double word boundary.

5. The method of claim 4 wherein the operands may alternatively be stored in the memory as contiguous zoned (eight-bit ASCII or EBCDIC coded numbers) which may begin and end on any eight-bit boundary within a word and wherein the instructions have provision for specifying the type of each operand as packed or zoned, said method further including the step of selecting four least significant bits of every eight-bit ASCII or EBCDIC byte received in the double word retrieved from the memory in response to a zoned type specification and transferring said four least significant bits to the first register means as a BCD digit.

6. The method of claim 5 wherein the operands further include leading signs or trailing signs and the instructions have provision for specifying each operand'"'"'s type as one of packed unsigned, packed with trailing sign, zoned unsigned, zoned with leading sign, or zoned with trailing sign.