Program/erase selection for flash memory

• US 5,053,990 A
• Filed: 02/17/1988
• Issued: 10/01/1991
• Est. Priority Date: 02/17/1988
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wells, Steven, Hoekstra, George, Baker, Alan, Kreifels, Jerry A., Winston, Mark, Kynett, Virgil N.
• Primary Examiner(s): Gossage, Glenn
• Assistant Examiner(s): LOOMIS, JOHN C
• Application Number:
  US07/157,361
• Time in Patent Office: 1,322 Days
• Field of Search: 364/200, 364/900, 365/201, 365/189
• US Class Current: 711/103
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A semiconductor flash EPROM/EEPROM device which includes a command port for receiving instruction on a data line and providing control signals to a memory for providing program and erase functions, a method to program and erase the memory. A program sequence is comprised of setting up a program command during a first write cycle, preforming a second write cycle to load address to address register and data to to a data register, programming during a program cycle and writing a program verify command during a third write cycle to verify the programmed data during a read cycle. An erase sequence is comprised of writing a setup erase command during a first write cycle, an erase command during a second write cycle providing the erasure during an erase cycle, writing the erase verify command during a third write cycle which also addresses the address of the memory and providing erase verification during a read cycle. Both the erase and program cycles provide for measured incremental erasing and programming.

Claims

1. An improved type of erasable and programmable read-only memory fabricated on a silicon substrate and employing a plurality of memory cells each of which has a floating gate and employing fixed numbers of data, address and control lines, wherein said data lines provide a bus for transporting data to and from said memory cells, wherein the improvement comprises using said fixed number of data lines to enter program and erase instructions as data to a port controller on said substrate, said port controller generating appropriate control signals for programming and erasing said memory cells electrically, said erasing accomplished by a method comprising the steps of:

(a) writing an erase setup command to said port controller during a first write cycle, said command originating from a microprocessor;

(b) writing an erase command to said port controller during a second write cycle, said command originating from said microprocessor;

(c) erasing said memory cells using an erase pulse during an erase cycle by one of said control signals from said port controller, said erase pulse having a predetermined pulsewidth;

(d) writing an erase verify command to said port controller during a third write cycle and providing a designated address to access a location in said memory, said command and address location originating from said microprocessor;

(e) generating verify voltages in said memory for reading contents of said location in memory, said verify voltages acting as reference voltages set to a predetermined level, such that said contents of said location are compared with said verify voltages to determine if said location is erased, said verify voltages generated under control of said port controller; and

if said location is not erased then incrementing said pulsewidth of said erase pulse of said erase cycle and under control of said microprocessor repeating steps (a) through (e) until said location is erased;

(f) repeating steps (d) and (e) until all address locations are erased and verified.

2. The method defined in claim 1, wherein if said erase cycle exceeds a predetermined length, said port controller produces an error message for said microprocessor.

3. The method defined in claim 2, wherein an address register maintains location of last location verified in step (e) to prevent duplicating verification of verified locations, said location being incremented and stored in said address register under control of said port controller.

4. An improved type of erasable and programmable read-only memory fabricated on a silicon substrate and employing a plurality of memory cells each of which has a floating gate and employing fixed numbers of data, address and control lines, wherein said data lines provide a bus for transporting data to and from said memory cells, wherein the improvement comprises using said fixed number of data lines to enter program and erase instructions as data to a port controller on said substrate, said port controller generating appropriate control signals for programming and erasing said memory cells electrically, said programming accomplished by a method comprising the steps of:

(1a) writing a programming set-up command to said port controller during a first write cycle, said command originating from a microprocessor;

(1b) latching address and data to said memory during a second write cycle by one of said control signals from said port controller;

(1c) programming said memory during a programming cycle by one of said control signals from said port controller;

(1d) writing a program verify command to said port controller during a third write cycle, said command originating from said microprocessor;

(1e) generating verify voltages in said memory for reading contents from a memory location in which data was programmed in step (1c), said verify voltages acting as reference voltages set to a predetermined level, such that said contents of said location are compared with said verify voltages to verify its contents, said verify voltages generated under control of said port controller; and

if said location is not programmed, then under control of said microprocessor repeating steps (1a) through (1e) until said location is programmed;

(1f) repeating steps (1a) through (1e) for a new address until all address locations are programmed and verified, the programmed locations being incremented and stored in a memory location under control of said port controller.

5. An improved type of erasable and programmable read-only memory fabricated on a silicon substrate and employing a plurality of memory cells each of which has a floating gate and employing fixed numbers of data, address and control lines, wherein said data lines provide a bus for transporting data to and from said memory cells, wherein the improvement comprises using said fixed number of data lines to enter program and erase instructions as data to a port controller on said substrate, said port controller generating appropriate control signals for programming and erasing said memory cells electrically, said erasing and programming accomplished by a method comprising the steps of:

(1a) writing an erase setup command to said port controller during a first write cycle, said command originating from a microprocessor;

(1b) writing an erase command to said port controller during a second write cycle, said command originating from said microprocessor;

(1c) erasing said memory cells using an erase pulse during an erase cycle by one of said control signals from said port controller, said erase pulse having a predetermined pulsewidth;

(1d) writing an erase verify command to said port controller during a third write cycle and providing a designated address to access a location in said memory, said command and address originating from said microprocessor;

(1e) generating verify voltages in said memory for reading contents of said location in memory, said verify voltages acting as reference voltages set to a predetermined level, such that said contents of said location are compared with said verify voltages to determine if said location is erased, said voltages generated under control of said port controller; and

if said location is not erased then incrementing said pulsewidth of said erase pulse of said erase cycle and under control of said microprocessor repeating steps (1a) through (1e) until said location is erased;

(1f) repeating steps (1d) and (1e) until all address locations are erased and verified, the erased locations being incremented and stored in a memory location under control of said port controller;

(2a) writing a programming set-up command to said port controller during a fourth write cycle, said command originating from said microprocessor;

(2b) latching address and data to said memory during a fifth write cycle by one of said control signals from said port controller;

(2c) programming said memory during a programming cycle by one of said control signals from said port controller;

(2d) writing a program verify command to said port controller during a sixth write cycle, said command originating from said microprocessor;

(2e) generating verify voltages in said memory for reading contents from a memory location in which data was programmed in step (2c), said verify voltages acting as reference voltages set to a predetermined level, such that said contents of said location are compared with said verify voltages to verify its contents, said voltages generated under control of said port controller; and

if said location is not programmed, then under control of said microprocessor repeating steps (2a) through (2e) until said location is programmed;

(2f) repeating steps (2d) through (2e) for a new address until all address locations are programmed and verified, the programmed locations being incremented and stored in a memory location under control of said port controller.

6. An improved type of erasable and programmable read-only memory fabricated on a silicon substrate and employing a plurality of memory cells each of which has a floating gate and employing fixed numbers of data, address and control lines, wherein said data lines provide a bus for transporting data to and from said memory cells, wherein the improvement comprises using said fixed number of data lines to enter program and erase instructions as data to a port controller on said substrate, said port controller generating appropriate control signals for preconditioning, programming and erasing said memory cells electrically, said preconditioning, erasing and programming accomplished by a method comprising the steps of:

(1) preconditioning said memory by programming bytes of said memory to a predetermined value to prevent over-erasing;

(2a) writing an erase setup command to said port controller during a first write cycle, said command originating from a microprocessor;

(2b) writing an erase command to said port controller during a second write cycle, said command originating from said microprocessor;

(2c) erasing said memory cells using an erase pulse during an erase cycle by one of said control signals from said port controller, said erase pulse having a predetermined pulsewidth;

(2d) writing an erase verify command to said port controller during a third write cycle and providing a designated address to access a location in said memory, said command and address location originating from said microprocessor;

(2e) generating verify voltages in said memory for reading contents of said location in memory, said verify voltages acting as reference voltages set to a predetermined level, such that said contents of said location are compared with said verify voltages to determine if said location is erased, said voltages generated under control of said port controller; and

if said location is not erased then incrementing said pulsewidth of said erase pulse of said erase cycle and under control of said microprocessor repeating steps (2a) through (2e) until said location is erased;

(2f) repeating steps (2d) and (2e) until all address locations are erased and verified, the erased locations being incremented and stored in a memory location under control of said port controller;

(3a) writing a programming setup command to said port controller during a fourth write cycle, said command originating from said microprocessor;

(3b) latching address and data to said memory during a fifth write cycle by one of said control signals from said port controller;

(3c) programming said memory during a programming cycle by one of said control signals from said port controller;

(3d) writing a program verify command to said port controller during a sixth write cycle, said command originating from said microprocessor;

(3e) generating verify voltages in said memory for reading contents from a memory location in which data was programmed in step (3c), said verify voltages acting as reference voltages set to a predetermined level, such that said contents of said location are compared with said verify voltages to verify its contents, said voltages generated under control of said port controller; and

if said location is not programmed, then under control of said microprocessor repeating steps (3a) through (3e) until said location is programmed;

(3f) repeating steps (3a) through (3e) for a new address until all address locations are programmed and verified, the programmed locations being incremented and stored in a memory location under control of said port controller.