Dual state memory storage cell with improved data transfer circuitry
First Claim
1. A dual storage cell, comprising:
- a first memory cell, comprising;
first and second cross-coupled inverters, driving first and second data nodes, respectively; and
an isolation circuit, having a conduction path coupled between said first and second cross-coupled inverters and a first power supply node, and having a control terminal;
a second memory cell, comprising;
first and second cross-coupled inverters, driving first and second data nodes, respectively; and
a first transfer circuit, comprising;
a first series circuit coupled between the first data node of said first memory cell and a second power supply node, having a control terminal for receiving a transfer enable signal enabling said first series circuit to couple said second power supply node to said first data node of said first memory cell, responsive to the data state of said second memory cell; and
a second series circuit coupled between the second data node of said first memory cell and said second power supply node, having a control terminal for receiving a transfer enable signal enabling said second series circuit to couple said second power supply node to said second data node of said first memory cell, responsive to the data state of said second memory cell;
wherein said control terminal of said isolation circuit is controlled in such a manner as to isolate said first and second cross-coupled inverters from said first power supply node during a portion of the time that said transfer enable signal enables said first and second series circuits.
1 Assignment
0 Petitions
Accused Products
Abstract
A dual storage cell is disclosed, which utilizes memory cells of cross-coupled inverters together with isolation transistors coupled between the driver transistors of the inverters and the reference supply node. Transfer circuitry is included in the dual storage cell, which couples one of the data nodes of the destination memory cell to a power supply node responsive to a transfer enable signal, and responsive to the data state of the source memory cell. During the transfer operation, the isolation transistors in the destination cell are turned off so that the cross-coupled inverters are not biased to the reference supply node. This allows the data transfer to occur without a DC current path between the power supply node and the reference supply node. The preferred implementation uses complementary transistors for the isolation transistors relative to the transfer devices, and to connect the gates together to the transfer enable signal. Either single or dual isolation transistors may be used in the memory cell, depending on layout constraints.
32 Citations
20 Claims
-
1. A dual storage cell, comprising:
-
a first memory cell, comprising; first and second cross-coupled inverters, driving first and second data nodes, respectively; and an isolation circuit, having a conduction path coupled between said first and second cross-coupled inverters and a first power supply node, and having a control terminal; a second memory cell, comprising; first and second cross-coupled inverters, driving first and second data nodes, respectively; and a first transfer circuit, comprising; a first series circuit coupled between the first data node of said first memory cell and a second power supply node, having a control terminal for receiving a transfer enable signal enabling said first series circuit to couple said second power supply node to said first data node of said first memory cell, responsive to the data state of said second memory cell; and a second series circuit coupled between the second data node of said first memory cell and said second power supply node, having a control terminal for receiving a transfer enable signal enabling said second series circuit to couple said second power supply node to said second data node of said first memory cell, responsive to the data state of said second memory cell; wherein said control terminal of said isolation circuit is controlled in such a manner as to isolate said first and second cross-coupled inverters from said first power supply node during a portion of the time that said transfer enable signal enables said first and second series circuits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A method of transferring data from a first memory cell to a second memory cell in a dual storage cell, said second memory cells comprising first and second cross-coupled inverters biased between first and second power supply nodes, and having first and second data nodes, comprising the steps of:
-
disconnecting said first and second cross-coupled inverters from being biased by said second power supply node; writing data to said second memory cell according to the contents of said first memory cell, comprising the steps of; coupling said first data node to said first power supply node responsive to said first memory cell storing a first data state; and coupling said second data node to said first power supply node responsive to said first memory cell storing a second data state; and after said writing step, connecting said first and second cross-coupled inverters to be biased by said second power supply node. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
-
Specification