Apparatus for scrambling/descrambling data by word-by-word processing

• US 5,054,069 A
• Filed: 08/28/1990
• Issued: 10/01/1991
• Est. Priority Date: 03/09/1989
• Status: Expired due to Term

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Maeno, Takahiro, Sato, Yasunori
• Primary Examiner(s): Tarcza, Thomas H.
• Assistant Examiner(s): CAIN, DAVID C
• Application Number:
  US07/574,147
• Time in Patent Office: 399 Days
• Field of Search: 380/49, 380/50
• US Class Current: 380/265
• CPC Class Codes: H04L 25/03872 Parallel scrambling or descrambling

Abstract

A scrambling/descrambling apparatus has a data memory for storing a data word, a bit invert flag, and numerical data. A bit shift operating section performs, on receiving a bit of data to be outputted or a bit of input data, a bit shift operation with that bit and stores resultant data in the data memory in the form of a first data word. A randomizing/derandomizing section randomizes or derandomizes the input data by using the first data word and based on a generating polynomial and, depending on a state represented by the bit invert flag, inverts the bit of the data to be outputted to develop output data. A count processing section increments or decrements the numerical value stored in the data memory and, depending on the numerical value, selectively sets the bit invert flag to a predetermined state. A count controlling section replaces the numerical value with a predetermined initial value on the basis of the first data word and bit invert flag. The data memory holds a second and a third data word, bits of which corresponding in position to a particular bit of the first data word are a ZERO and a ONE, respectively. The count controlling section reads selectively either one of the second and third data words out of the data memory depending on the value of the bit which is inputted to the bit shift operating section, Exclusive-ORs the data word read out and the first data word, performs a masking operation with a data word resulting from the Exclusive-ORing for validating a bit corresponding in position to the particular bit position of the first data word while invalidating the remaining bits, and replaces the numerical value with the initial value when a data word resulting from the masking operation is indicative of a ZERO or when the bit invert flag is in the predetermined state. Alternatively, the count controlling section may read the first data word out of the data memory and, depending on the value of the bit which is inputted to the bit shift operating section, NOT or transfer the first data word, performs a masking operation with a data word representative of a result of NOTing or that of transfer for validating a bit corresponding in position to the particular bit position of the first data word while invalidating the remaining bits, and replace the numerical value with the initial value when a data word resulting from the masking operation is indicative of a ZERO or when the bit invert flag is in the predetermined state.

Claims

1. A scrambling/descrambling apparatus for scrambling/descrambling input data to produce output data comprising:

storing means for storing a data word, a bit invert flag, and numerical data;

bit shift operating means for performing, on receiving a bit of data to be outputted or a bit of input data, a bit shift operation with said bit and storing resultant data in said storing means in a form of a first data word;

randomizing/derandomizing means for randomizing or derandomizing the input data by using said first data word and based on a generating polynomial and, depending on a state represented by said bit invert flag, inverting said bit of said data to be outputted to develop output data;

count processing means for incrementing or decrementing the numerical value stored in said storing means and, depending on said numerical value, selectively setting said bit invert flag to a predetermined state; and

count controlling means for replacing said numerical value with a predetermined initial value on the basis of said first data word and said bit invert flag;

said storing means holding a second and a third data word, bits of which corresponding in position to a particular bit of said first data word are a ZERO and a ONE, respectively;

said count controlling means

reading selectively either one of said second and third data words out of said storing means depending on the value of said bit which is inputted to said bit shift operating means;

Exclusive-ORing said data word read out and said first data word;

performing a masking operation with a data word resulting from the Exclusive-ORing for validating a bit corresponding in position to said particular bit position of said first data word while invalidating the remaining bits;

replacing said numerical value with said initial value when a data word resulting from the masking operation is indicative of a ZERO or when said bit invert flag is in said predetermined state.

2. An apparatus in accordance with claim 1, wherein said randomizing/derandomizing means inverts said bit of said data to be outputted in response to an indication TRUE of said bit invert flag;

said count processing means setting selectively said bit invert flag to either one of TRUE and FALSE on the basis of said numerical value stored in said storing means;

said count controlling means reading said third and second data words out of said storing means in response to a ZERO and a ONE, respectively, which are inputted to said bit shift operating means, and replacing said numerical value with said initial value when said data word resulting from said masking operation is indicative of ZERO or when said bit invert flag is indicative of TRUE.

3. An apparatus in accordance with claim 1, further comprising an input terminal to be interconnected to a modem of a phase modulation system for receiving the input data from said modem;

and

an output terminal to be interconnected to said modem for delivering the output data to the modem;

each of said data words having sixteen bits;

said randomizing/derandomizing means using a generating polynomial 1+x^-6 +x^-7 ;

said count controlling means handling the eighth, ninth and twelfth bit positions of said data words as said predetermined bit position.

4. An apparatus in accordance with claim 1, further comprising a modem for producing input data by demodulating a signal and modulating output data by a phase modulation system.

8. A scrambler in accordance with claim 1, further comprising a modulator for producing input data by modulating output data by a phase modulation system.

5. A scrambler for scrambling input data to produce output data, comprising:

storing means for storing a data word, a bit invert flag, and numerical data;

bit shift operating means for performing, on receiving a bit of data to be outputted, a bit shift operation with said bit and storing resultant data in said storing means in a form of a first data word;

randomizing means for randomizing input data by using said first data word and based on a generating polynomial and, depending on a state represented by said bit invert flag, inverting said bit of said data to be outputted to develop output data;

count processing means for incrementing or decrementing the numerical value stored in said storing means and, depending on said numerical value, selectively setting said bit invert flag to a predetermined state; and

count controlling means for replacing said numerical value with a predetermined initial value on the basis of said first data word and said bit invert flag;

said storing means holding a second and a third data word, bits of which corresponding in position to a particular bit of said first data word are a ZERO and a ONE, respectively;

said count controlling means

reading selectively either one of said second and third data words out of said storing means in association with the value of said bit which is inputted to said bit shift operating means;

Exclusive-ORing said data word and said first data word;

performing a masking operation with a data word resulting from the Exclusive-ORing for validating a bit corresponding in position to said particular bit position of said first data word while invalidating the remaining bits;

replacing said numerical value with said initial value when a data word resulting from the masking operation is indicative of a ZERO or when said bit invert flag is in said predetermined state.

6. A scrambler in accordance with claim 5, wherein said randomizing means inverts said bit of said data to be outputted in response to an indication TRUE of said bit invert flag;

said count processing means selectively setting said bit invert flag to either one of TRUE and FALSE on the basis of said numerical value stored in said storing means;

said count controlling means reading said third and second data words out of said storing means in response to a ZERO and a ONE, respectively, which are inputted to said bit shift operating means, and replacing said numerical value with said initial value when said data word resulting from the masking operation is indicative of a ZERO or when said bit invert flag is TRUE.

7. A scrambler in accordance with claim 5, further comprising:

an input terminal to be connected to a modulator of a phase modulation system for receiving input data from said modulator; and

an output terminal to be connected to said modulator for delivering output data to said modulator;

each of said data words having sixteen bits;

said randomizing means using a generating polynomial 1+x^-6 +x^-7 ;

said count controlling means handling the eighth, ninth and twelfth bit positions of said data words as said predetermined bit position.

9. A descrambler for descrambling input data to produce output data comprising:

storing means for storing a data word, a bit invert flag, and numerical data;

bit shift operating means for performing, on receiving a bit of input data, a bit shift operation with said bit and storing resultant data in said storing means in a form of a first data word;

derandomizing means for derandomizing the input data by using said first data word and based on a generating polynomial and, depending on a state represented by said bit invert flag, inverting a bit of data to be outputted to develop output data;

count processing means for incrementing or decrementing the numerical value stored in said storing means and, depending on said numerical value, selectively setting said bit invert flag to a predetermined state; and

count controlling means for replacing said numerical value with a predetermined initial value on the basis of said first data word and said bit invert flag;

said storing means holding a second and a third data word, bits of which corresponding in position to a particular bit of said first data word are a ZERO and a ONE, respectively;

said count controlling means

reading selectively either one of said second and third data words out of said storing means in association with the value of said bit which is inputted to said bit shift operating means;

Exclusive-ORing said data word and said first data word;

performing a masking operation with a data word resulting from the Exclusive-ORing for validating a bit corresponding in position to said particular bit position of said first data word while invalidating the remaining bits;

replacing said numerical value with said initial value when a data word resulting from the masking operation is indicative of a ZERO or when said bit invert flag is in said predetermined state.

10. A descrambler in accordance with claim 9, wherein said derandomizing means inverts said bit of said data to be outputted in response to an indication TRUE of said bit invert flag;

said count processing means setting selectively said bit invert flag to either one of TRUE and FALSE on the basis of said numerical value stored in said storing means;

said count controlling means reading said third and second data words out of said storing means in response to a ZERO and a ONE, respectively, which are inputted to said bit shift operating means, and replacing said numerical value with said initial value when said data word resulting from the masking operation is indicative of a ZERO or when said bit invert flag is indicative of TRUE.

11. A descrambler in accordance with claim 9, further comprising:

an input terminal connected to a demodulator of a phase modulation system for receiving input data from said demodulator; and

an output terminal to be connected to said demodulator for delivering output data to said demodulator;

each of said data words having sixteen bits;

said derandomizing means using a generating polynomial 1+x^-6 +x^-7 ;

said count controlling means handling the eighth, ninth and twelfth bit positions of said data words as said predetermined bit position.

12. A descrambler in accordance with claim 9, further comprising a demodulator for producing input data by demodulating output data by a phase modulation system.

13. A scrambling/descrambling apparatus for scrambling/descrambling input data to produce output data, comprising:

storing means for storing a data word, a bit invert flag, and numerical data;

bit shift operating means for performing, on receiving a bit of data to be outputted or a bit of input data, a bit shift operation with said bit and storing resultant data in said storing means in a form of a first data word;

randomizing/derandomizing means for randomizing or derandomizing the input data by using said first data word and based on a generating polynomial and, depending on a state represented by said bit invert flag, inverting said bit of said data to be outputted to develop output data;

count processing means for incrementing or decrementing the numerical value stored in said storing means and, depending on said numerical value, selectively setting said bit invert flag to a predetermined state; and

count controlling means for replacing said numerical value with a predetermined initial value on the basis of said first data word and said bit invert flag;

said storing means holding said first data word;

said count controlling means

reading said first data word out of said storing means and, depending on the value of said bit which is inputted to said bit shift operating means, NOTing or transferring said first data word;

performing a masking operation with a data word representative of a result of said NOTing or said transfer for validating a bit corresponding in position to said particular bit position of said first data word while invalidating the remaining bits;

replacing said numerical value with said initial value when a data word resulting from said masking operation is indicative of a ZERO or when said bit invert flag is in said predetermined state.

14. An apparatus in accordance with claim 13, wherein said randomizing/derandomizing means inverts said bit of said data to be outputted in response to an indication TRUE of said bit invert flag;

said count processing means setting selectively said bit invert flag to either one of TRUE and FALSE on the basis of said numerical value stored in said storing means;

said count controlling means reading said first data word out of said storing means and, in response to a ZERO and a ONE, respectively, which are inputted to said bit shift operating means, NOTing said first data word and transferring said first data word;

replacing said numerical value with said intial value when a data word representative of a result of said masking operation is indicative of a ZERO or when said bit invert flag is TRUE.

15. An apparatus in accordance with claim 13, further comprising

an input terminal to be interconnected to a modem of a phase modulation system for receiving the input data from said modem;

and

an output terminal to be interconnected to said modem for delivering the output data to the modem;

each of said data words having sixteen bits;

said randomizing/derandomizing means using a generating polynomial 1+x^-6 +x^-7 ;

said count controlling means handling the eighth, ninth and twelfth bit positions of said data words as said predetermined bit position.

16. An apparatus in accordance with claim 13, Characterized BY a modem (5) for producing input data by demodulating a signal and modulating output data by a phase modulation system.

17. A scrambler for scrambling input data to produce output data, comprising:

storing means for storing a data word, a bit invert flag, and numerical data;

bit shift operating means for performing, on receiving a bit of data to be outputted, a bit shift operation with said bit and storing resultant data in said storing means in a form of a first data word;

randomizing means for randomizing input data by using said first data word and based on a generating polynomial and, depending on a state represented by said bit invert flag, inverting said bit of said data to be outputted to develop output data;

count processing means for incrementing or decrementing the numerical value stored in said storing means and, depending on said numerical value, selectively setting said bit invert flag to a predetermined state; and

count controlling means for replacing said numerical value with a predetermined initial value on the basis of said first data word and said bit invert flag;

said storing means holding said first data word;

said count controlling means

reading said first data word out of said storing means and, depending on the value of said bit which is inputted to said bit shift operating means, NOTing or transferring said first data word;

performing a masking operation with a data word representative of a result of said NOTing or said transfer for validating a bit corresponding in position to said particular bit position of said first data word while invalidating the remaining bits;

replacing said numerical value with said initial value when a data word resulting from the masking operation is indicative of a ZERO or when said bit invert flag is in said predetermined state.

18. A scrambler in accordance with claim 17, wherein said randomizing means inverts said bit of said data to be outputted in response to an indication TRUE of said bit invert flag;

said count processing means selectively setting said bit invert flag to either one of TRUE and FALSE on the basis of said numerical value stored in said storing means;

said count controlling means reading said first data word out of said storing means and, in response to a ZERO and a ONE, respectively, which are inputted to said bit shift operating means, NOTing said first data word and transferring said first data word;

replacing said numerical value with said initial value when said data word representative of a result of said masking operation is indicative of a ZERO or when said bit invert flag is TRUE.

19. A scrambler in accordance with claim 17, further comprising:

an input terminal to be connected to a modulator of a phase modulation system for receiving input data from said modulator; and

an output terminal to be connected to said modulator for delivering output data to said modulator;

each of said data words having sixteen bits;

said randomizing means using a generating polynomial 1+x^-6 +x^-7 ;

said count controlling means handling the eighth, ninth and twelfth bit positions of said data words as said predetermined bit position.

20. A scrambler in accordance with claim 17, further comprising a modulator for producing input data by modulating output data by a phase modulation system.

21. A descrambler for descrambling input data to produce output data, comprising:

storing means for storing a data word, a bit invert flag, and numerical data;

bit shift operating means for performing, on receiving a bit of input data, a bit shift operation with said bit and storing resultant data in said storing means in a form of a first data word;

derandomizing means for derandomizing the input data by using said first data word and based on a generating polynomial and, depending on a state represented by said bit invert flag, inverting a bit of data to be outputted to develop output data;

count processing means for incrementing or decrementing the numerical value stored in said storing means and, depending on said numerical value, selectively setting said bit invert flag to a predetermined state; and

count controlling means for replacing said numerical value with a predetermined initial value on the basis of said first data word and said bit invert flag;

said storing means holding said first data word;

said count controlling means

reading said first data word out of said storing means and, depending on the value of said bit which is inputted to said bit shift operating means, NOTing or transferring said first data word;

performing a masking operation with a data word representative of a result of said NOTing or said transfer for validating a bit corresponding in position to said particular bit position of said first data word while invalidating the remaining bits;

replacing said numerical value with said initial value when a data word resulting from the masking operation is indicative of a ZERO or when said bit invert flag is in said predetermined state.

22. A descrambler in accordance with claim 21, wherein said derandomizing means inverts said bit of said data to be outputted in response to an indication TRUE of said bit invert flag;

said count processing means setting selectively said bit invert flag to either one of TRUE and FALSE on the basis of said numerical value stored in said storing means;

said count controlling means reading said first data word out of said storing means and, in response to a ZERO and a ONE, respectively, which are inputted to said bit shift operating means, NOTing said first data word and transferring said data word;

replacing said numerical value with said initial value when a data word representative of a result of said masking operation is indicative of a ZERO or when said bit invert flag is TRUE.

23. A descrambler in accordance with claim 21, further comprising:

an input terminal connected to a demodulator of a phase modulation system for receiving input data from said demodulator; and

an output terminal to be connected to said demodulator for delivering output data to said demodulator;

each of said data words having sixteen bits;

said derandomizing means using a generating polynomial 1+x^-6 +x^-7 ;

said count controlling means handling the eighth, ninth and twelfth bit positions of said data words as said predetermined bit position.

24. A descrambler in accordance with claim 21, further comprising a demodulator for producing input data by demodulating output data by a phase modulation system.