Active matrix type liquid crystal display

• US 5,054,887 A
• Filed: 08/09/1989
• Issued: 10/08/1991
• Est. Priority Date: 08/10/1988
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Kato, Hiroaki, Hibino, Yoshitaka, Hirobe, Toshihiko
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Crane, Sara W.
• Application Number:
  US07/391,244
• Time in Patent Office: 790 Days
• Field of Search: 350/334, 350/336, 350/339 R, 357/23.7, 357/54
• US Class Current: 349/42
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode

Abstract

An active matrix type liquid crystal display device includes a substrate on which a matrix picture element electrodes reside, TFTs which are disposed in the vicinity of each picture element electrodes, and capacitor electrodes are provided, each of which is opposed to one portion of each of the picture element electrodes. A dielectric lamination structure consisting of three insulating layers is formed between the picture element electrode and the capacitor electrode. The dielectric lamination structure includes an anodic oxidation film, a gate insulating layer and a protective insulating layer. The protective insulating layer further extending over the associated TFT.

Claims

1. An active matrix type liquid crystal display device comprising:

a substrate;

a plurality of picture element electrodes arranged in a matrix on said substrate;

a plurality of switching elements, each of said picture element electrodes being associated with a picture element electrode;

capacitor electrodes, each of said picture element electrodes being partially opposed to at least one capacitor electrode to form a capacitor; and

a dielectric lamination structure consisting essentially of three insulating layers between said picture element electrode and said capacitor electrode, a first insulating layer extending over the associated switching element to provide protection thereto.

2. The device of claim 1 wherein said substrate is insulating and said switching element is a thin film transistor, a gate electrode of said thin film transistor and said capacitor electrode being disposed on the insulating substrate, and a gate insulating layer being formed on both said gate electrode and said capacitor electrode, said gate insulating layer being one of said three laminated insulating layers.

3. The device of claim 2 wherein a protective insulating layer is the first insulating layer and is formed on both said thin film transistor and said gate insulating layer, said protective insulating layer being another one of said three laminated insulating layers.

4. The device of claim 3 wherein an anodic oxidation film is formed on said capacitor electrode, said anodic oxidation film being the further one of said three laminated insulating layer.

5. The device of claim 3 wherein said picture element electrode is disposed on said protective insulating layer.

6. The device of claim 5 wherein said picture element electrode is electrically connected to the drain electrode of said TFT, through a contact hole which is formed in said protective insulating layer.

7. The device of claim 2, wherein a protective insulating layer is the first insulating layer formed on both said thin film transistor and said gate insulating layer and said picture element electrode is connected to the drain electrode of said thin film transistor through a hole formed on said protective insulating layer, said protective insulating layer being another one of said three laminated layers.

8. The device of claim 3 wherein said protective insulating layer extends under said picture element electrode.

9. A substrate assembly for use in a flat panel display device in cooperation with a display material and a second assembly having at least one picture element electrode, said substrate assembly comprising:

a substrate;

a picture element electrode provided on said substrate, for cooperation with the picture element electrode of said another assembly;

a thin film transistor formed on said substrate and driving said picture element;

a protective insulating layer overlaying said thin film transistor to provide protection therefor;

a capacitor electrode provided on said substrate and underlying said picture element electrode; and

,

a dielectric lamination structure having at least two insulative layers disposed between said picture element electrode and said capacitor electrode to provide electrical isolation therebetween;

said protective insulating layer extending over said capacitor electrode and under said picture element electrode to further form one of said insulative layers of said dielectric lamination structure and contribute to the electrical isolation provided thereby.

10. The substrate assembly of claim 9 wherein said thin film transistor includes a gate separated from a source and drain by a gate insulating layer, said gate insulating layer forming one of said at least two insulating layers.

11. The substrate assembly of claim 10 wherein said dielectric lamination layer further includes an anodic oxidation film formed on said capacitor electrode, said oxidation film further being formed on said gate of said thin film transistor.

12. The substrate assembly of claim 9 wherein said flat panel display device is a liquid crystal display device and said display material is a liquid crystal material.

13. A substrate assembly for use in a matrix flat panel display device in cooperation with a display material and a second assembly having at least one picture element electrode, said substrate assembly comprising:

a substrate;

a plurality of picture element areas each including a picture element electrode provided on said substrate, for cooperation with the picture element electrode of said another assembly, each picture element area further including,

a thin film transistor formed on said substrate and driving said picture element electrode;

a protective insulating layer overlaying said thin film transistor to provide protection therefor;

a capacitor electrode provided on said substrate and underlying said picture element electrode; and

,

a dielectric lamination structure having at least two insulative layers disposed between said picture element electrode and said capacitor electrode to provide electrical isolation therebetween;

said protective insulating layer extending over said capacitor electrode and under said picture element electrode to further form one of said insulative layers of said dielectric lamination structure and contribute to the electrical isolation provided thereby.