Photo-sensor cell suitable for IC chip

• US 5,055,668 A
• Filed: 03/22/1990
• Issued: 10/08/1991
• Est. Priority Date: 05/24/1989
• Status: Expired due to Fees

• Current Assignee: Nissan Motor Co., Ltd.
• Original Assignee: Nissan Motor Co., Ltd.
• Inventors: French, Patrick J.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Messinger, Michael
• Application Number:
  US07/497,314
• Time in Patent Office: 565 Days
• Field of Search: 250/213 A, 250/208.4, 250/208.5, 250/208.2, 307/311
• US Class Current: 250/208.2
• CPC Class Codes: G01D 5/26 characterised by optical transfer means, i.e. using infrared, visible, or ultraviolet light
• CPC Class Codes: H03K 17/943 using a plurality of optical emitters or detectors, e.g. keyboard
• CPC Class Codes: H03K 3/0377 Bistables with hysteresis, e.g. Schmitt trigger non-regenerative amplitude discriminators G01R19/165
• CPC Class Codes: H03K 3/286 bistable
• CPC Class Codes: H03K 3/356 Bistable circuits

Abstract

The photo-sensor cell comprises two optical flip-flop sensors having two different light intensity thresholds, respectively , under imbalanced load offset conditions, two logic cells for latching only two different binary level signals from the two optical sensor respectively, without latching two of the same binary level signals from the two optical sensors due to a high or low pulsed power supply, and an output logic cell for generating an output binary signal from the time when light intensity rises beyond a higher threshold to the time when it drops below a lower threshold. Since all the elements are standardized in an IC manufacturing process and further no synchronizing clock signals are required between cells and signal processing logic owing to latch operations when a number of cells are connected in series or parallel, it is possible to realize a compact digital photo-sensor cell assembly with hysteresis activated by a pulsed power supply.

Claims

1. A photo-sensor cell, comprising:

(a) first light sensing means for generating two different switched digital level signals when incident light rises beyond or drops below a first threshold;

(b) second light sensing means for generating two different switched digital level signals when said incident light rises beyond or drops below a second threshold higher than said first threshold;

(c) first latching means responsive to said first light sensing means, for latching only two different switched digital level signals without latching two of the same digital level signals;

(d) second latching means responsive to said second light sensing means, for latching only two different switched digital level signals without latching two of the same digital level signals; and

(e) output logic means responsive to said first and second latching means, for generating a digital output signal from a time when said incident light rises beyond said second threshold to a time when said incident light drops below said first threshold, and having a hysteresis loop for said digital output signal with respect to said incident light.

2. A photo-sensor cell, comprising:

(a) a first optical flip-flop sensor for generating two different first binary level signals from a pulsed supply voltage when an intensity of light allowed to be incident thereupon rises beyond or drops below a first incident light threshold (L₁), respectively;

(b) a second optical flip-flop sensor for generating two different second binary level signals from a pulsed supply voltage when said intensity of light allowed to be incident thereupon rises beyond or drops below a second incident light threshold (L₂) higher than said first threshold (L₁), respectively;

(c) a first logic cell responsive to said first optical flip-flop sensor, for latching said two different first binary level signals generated by said first optical flip-flop sensor as first latched signals and for generating two different binary level signals corresponding to said first latched signals and, when said first optical flip-flop sensor generates two of the same binary level signals simultaneously, said first logic cell keeping two preceding different binary level signals latched;

(d) a second logic cell responsive to said second optical flip-flop sensor for latching said two different second binary level signals generated by said second optical flip-flop sensor as second latched signals and for generating two different binary level signals corresponding to said second latched signals and, when said second optical flip-flop sensor generates two of the same binary level signals simultaneously, said second logic cell keeping two preceding different binary level signals latched; and

(e) an output logic cell responsive to said first and second logic cells for generating an output binary signal on the basis of said first and second latched signals of said first and second logic cells from a time when said intensity of light allowed to be incident upon said second optical flip-flop sensor rises beyond said second threshold (L₂) to a time when said intensity of light allowed to be incident upon said first optical flip-flop sensor drops below said first threshold (L₁), in such a way as to provide a hysteresis loop for said output binary signal with respect to said intensity of light for said photo-sensor cell.

3. The photo-sensor cell of claim 2, wherein each of said first and second optical flip-flop sensors comprises:

(a) a first switching element provided with a light sensing area; and

(b) a second switching element connected to said light switching element in cross-connection manner such that an input node of said first element is connected to an output node of said second element and vice versa under imbalanced load offset conditions, said first switching element being kept turned off and said second switching element being kept turned off when no light is allowed to be incident upon light sensing area of said first element, but said first and second switching elements being switched reversely when light is allowed to be incident upon said first element beyond a predetermined threshold.

4. The photo-sensor cell of claim 2, wherein each of said first and second optical flip-flop sensors comprises:

(a) a first switching element;

(b) a second switching element connected to said first switching element in cross-connection manner such that an input node of said first element is connected to an output node of said second element and vice versa, under imbalanced load resistor conditions; and

(c) a photodiode connected to an input node of said second switching element, said first switching element being kept turned off and said second switching element being kept turned off when no light is allowed to be incident upon said photodiode, but said first and second switching elements being switched reversely when light is allowed to be incident upon said photodiode beyond a predetermined threshold.

5. The photo-sensor cell of claim 2, wherein each of said first and second logic cells comprises:

(a) a first inverter responsive to a first binary level signal of said optical flip-flop sensor;

(b) a second inverter responsive to a second binary level signal to said optical flip-flop sensor;

(c) a first NOR gate connected to said first inverter and responsive to said second binary level signal of said optical flip-flop sensor;

(d) a second NOR gate connected to said second inverter and responsive to said first binary level signal of said optical flip-flop sensor; and

(e) a flip-flop latch composed of third and fourth NOR gates and connected to said first and second NOR gates, for latching two different binary level signals of said first and second NOR gates, respectively but keeping two preceding different latched binary level signals when said optical flip-flop sensor generates two of the same binary level signals simultaneously.

6. The photo-sensor cell of claim 2, wherein said output logic cell comprises:

(a) a first NOR gate responsive to two first binary level signals of said first and second logic cells;

(b) a second NOR gate responsive to two second binary level signals of said first and second logic cells; and

(c) a flip-flop latch composed of third and fourth NOR gates and connected to said first and second NOR gates, for generating an output binary signal when said intensity of light to said second optical flip-flop sensor rises beyond said second threshold and when said intensity of light to said first optical flip-flop sensor drops below said first threshold so as to provide a hysteresis loop characteristic for said output binary signal with respect to said intensity of light for said photo-sensor cell.

8. The photo-sensor cell of claim 2, wherein said first and second optical flip-flop sensors, said first and second logic cell and said output logic cells are configured into a single integrated circuit chip.

9. The photo-sensor cell of claim 2, wherein a number of photo-sensor cells are connected in series in an array state to detect a rectilinear position, without any synchronizing clock signals between said series-connected photo-sensor cells and additional external processing circuitry.

10. The photo-sensor cell of claim 2, wherein a number of the photo-sensor cells are connected in series in a ring state to detect an angular position, without any synchronizing clock signals between said ring-connected photosensor cells and additional external signal processing circuitry.

11. The photo-sensor cell of claim 2, wherein a number of photo-sensor cells are connected in series and parallel in an assembly to detect a coordinates position, without any synchronizing clock signals between said series and parallel connected photosensor cells and additional external signal processing circuitry.

7. A photo-sensor cell comprising:

(a) a first optical flip-flop sensor for generating first and second binary signals "0" and "1" at first and second output terminals thereof, respectively, when an intensity of light allowed to be incident thereupon rises beyond a first light intensity threshold (L₁), and second and first binary signals "1" and "0" at said first and second output terminals thereof, respectively, when said intensity of light allowed to be incident thereupon drops below said first light intensity threshold (L₁), said first sensor being activated by a pulsed supply voltage;

(b) a second optical flip-flop sensor for generating first and second binary signals "0" and "1" at first and second output terminals thereof, respectively, when an intensity of light allowed to be incident thereupon rises beyond a second light intensity threshold (L₂) higher than said first light intensity threshold (L₁) and second and first binary signals "1" and "0" at said first and second output terminals thereof, respectively, when said intensity of light allowed to be incident thereupon drops below said second light intensity threshold (L₂), said second sensor being activated by said pulsed supply voltage;

(c) a first logic cell connected to said first optical flip-flop sensor, for latching said binary signals generated from said first optical flip-flop sensor, and generated second and first binary signals "1" and "0" at first and second output terminals thereof, respectively, in response to said first and second binary signals "0" and "1" from said first and second terminals of said first optical flip-flop sensor and said first and second binary signals "0" and "1" from said first and second output terminals, respectively, in response to said second and first binary signals "1" and "0" of said first and second terminals of said first optical flip-flop sensor, when said first optical flip-flop sensor generates two of the same binary level signals "0" or "1", said first logic cell latching two preceding different binary level signals in response to said binary signals of said first optical flip-flop sensor;

(d) a second logic cell connected to said second optical flip-flop sensor, for latching said binary signals generated by said second optical cell, and generating second and first binary signals "1" and "0" from first and second output terminals thereof, respectively, in response to said first and second binary signals "0" and "1" from said first and second terminals of said second optical flip-flop sensor and said first and second binary signals "0" and "1" from said first and second output terminals thereof, respectively, in response to said second and first terminals of said second optical flip-flop sensor, when said first optical flip-flop sensor generates two of the same binary level signals "0" and "1", said second logic cell latching two preceding different binary level signals in response to said binary signals from said second optical flip-flop sensor; and

(e) an output logic cell connected to said first and second logic cells, for generating a second binary signal "0" in response to said second and first binary signals "1" and "1" of said first and second terminals of said first logic cell and said first and second terminals of said second logic cell, when said intensity of light rises beyond said second threshold L₂ of said second optical flip-flop sensor and drops below said first threshold L₁ of said first optical flip-flop sensor and a first binary signal "0" in response to said first and second binary signals "0" and "1" of said first and second terminals of said first logic cell and of said first and second terminals of said second logic cell when said intensity of light drops below said second threshold L₂ of said second optical flip-flop sensor and also below said first threshold L₁ of said first optical flip-flop sensor.