Image sensing and recording device having a multilayer analog memory stacked on an image sensing array

• US 5,055,930 A
• Filed: 09/07/1990
• Issued: 10/08/1991
• Est. Priority Date: 09/13/1989
• Status: Expired due to Term

• Current Assignee: Olympus Optical Corporation Limited (Olympus Corporation)
• Original Assignee: Olympus Optical Corporation Limited (Olympus Corporation)
• Inventors: Yamada, Hidetoshi, Nagasaki, Tatsuo
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): Metjahic, Safet
• Application Number:
  US07/579,784
• Time in Patent Office: 396 Days
• Field of Search: 358/213.11, 358/213.13, 358/213.33, 358/909, 358/213.31, 358/213.25, 358/213.27, 358/213.29, 358/212, 358/209, 352/24 LR, 352/30 I, 250/208.1
• US Class Current: 348/317
• CPC Class Codes: H01L 27/14812 Special geometry or disposition of pixel-elements, address lines or gate-electrodes
• CPC Class Codes: H04N 23/50 Constructional details
• CPC Class Codes: H04N 25/70 SSIS architectures; Circuits associated therewith
• CPC Class Codes: H04N 25/71 Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
• CPC Class Codes: H04N 25/72 using frame transfer [FT]

Abstract

An image sensing and recording device includes a light-receiving element array, an analog memory, and a transfer section which are integrally formed. The array has an image sensing surface on which a plurality of light-receiving elements are two-dimensionally arranged and generates signal charges by photoelectrically converting light images incident on the surface in units of the elements. The memory has a plurality of storage regions having a multilayer structure stacked on the array. The storage regions transfer the signal charges generated by the elements of the array in a stacked direction thereof and sequentially storing the signal charges. The transfer section is stacked to sandwich the memory between the transfer section and the array and is designed to read out the signal charges, which are sequentially stored in the memory, as time-serial image signals. A dark box incorporates the device. An optical lens is arranged in the dark box so as to form an object image on the surface of the device. A controller is arranged in the dark box so as to control generation of signal charges by the array of the device and to control transfer/storage of signal charges by the memory.

Claims

1. An image sensing and recording device comprising:

a light-receiving element array section, having an image sensing surface on which a plurality of light-receiving elements are two-dimensionally arranged, for generating signal charges by photoelectrically arranged, for generating signal charges by photoelectrically converting light images incident on said image sensing surface in units of said plurality of light-receiving elements;

an analog memory section having a plurality of storage regions staked vertically in a multilayer structure on said light-receiving element array section, said plurality of storage regions including means for transferring the signal charges generated by said plurality of light-receiving element of said light-receiving element array section in a stacked direction thereof and sequentially storing the signal charges; and

a transfer section, stacked to sandwich said analog memory section between said transfer section and said light-receiving element array section, for reading out the signal charges, which are sequentially stored in said analog memory section, as time-serial image signals.

2. A device according to claim 1, wherein said light-receiving element array section, said analog memory section, and said transfer section are realized as a semiconductor device having an element structure stacked and integrally formed on a predetermined semiconductor substrate.

3. A device according to claim 2, wherein said transfer section is formed as a charge transfer element group on said predetermined semiconductor substrate, said analog memory section is formed as a semiconductor memory cell group having a plurality of layers stacked on said charge transfer element group, and said light-receiving element array section is formed as a two-dimensionally arranged semiconductor light-receiving element group stacked on an uppermost layer portion of said semiconductor memory cell group having the plurality of layers.

4. A device according to claim 3, wherein said semiconductor memory cell group is constituted by a plurality of two-dimensional analog memories stacked as layers and having signal charge storage portions respectively corresponding to the elements of said semiconductor light-receiving element group.

5. A device according to claim 4, wherein said plurality of two-dimensional analog memories respectively include EEPROM cells.

6. A device according to claim 2, wherein said charge transfer element group includes CCD channels each constituted by an impurity layer of a second conductivity type formed on a semiconductor substrate of a first conductivity type, and a plurality of CCDs each constituted by a transfer gate electrode and a CCD electrode embedded in an insulating layer on each of said CCD channels.

7. A device according to claim 6, wherein each element of said semiconductor light-receiving element group includes a photodiode embedded between a layer of the second conductivity type and a layer of the first conductivity type, and a reset transistor constituted by said layer of the first conductivity type, said layer of the second conductivity type, and a gate electrode embedded in an insulating layer.

8. A device according to claim 5, wherein said EEPROM cells have a structure constituted by layers sequentially stacked on each other in a vertical direction, each of said layers including a control gate electrode having a floating gate formed therein, source and drain regions constituted by a layer of the second conductivity type embedded in a layer of the first conductivity type, and a load resistor, and said EEPROM cells being sequentially connected to each other through wiring interlayer electrodes in the vertical direction.

9. A device according to claim 4, wherein each of said two-dimensional analog memories includes a memory cell having an MNOS structure.

10. A device according to claim 1, wherein said analog memory section comprises a plurality of EEPROM cells as layers integrally stacked on said transfer section constituted by said charge transfer elements, and the signal charges from said light-receiving element array section integrally stacked on said analog memory section are parallelly transferred and stored in the direction of thickness in response to a control gate pulse supplied to each of said EEPROM cells.

11. A device according to claim 1, wherein said light-receiving element array section comprises a plurality of capacitors for respectively storing the signal charges generated by said plurality of light-receiving elements upon photoelectric conversion, said light-receiving element array section having an electronic shutter function realized by control of signal charge storage times of said capacitors.

12. An electronic still camera comprising:

an image sensing and recording device comprising;

a) a light-receiving element array section, having an image sensing surface on which a plurality of light-receiving elements are two-dimensionally arranged, for generating signal charges by photoelectrically converting light images incident on said image sensing surface in units of said plurality of light-receiving elements,

b) an analog memory section having a plurality of storage regions stacked vertically in a multilayer structure on said light-receiving element array section, said plurality of storage regions including means for transferring the signal charges generated by said plurality of light-receiving elements of said light-receiving element array section in a stacked direction thereof and sequentially storing the signal charges, and

c) a transfer section, stacked to sandwich said analog memory section between said transfer section and said light-receiving element array section, for reading out the signal charges, which are sequentially stored in said analog memory section, as time-serial image signals;

a dark box member incorporating said image sensing and recording device;

an optical lens arranged in said dark box member, for forming an object image on the image sensing surface of said image sensing and recording device; and

control means, arranged in said dark box member, for controlling generation of signal charges by said light-receiving element array section of said image sensing and recording device and controlling transfer/storage of signal charges by said analog memory section.

13. A camera according to claim 12, wherein said image sensing and recording device, said optical lens for forming an object image on the image sensing surface of said image sensing and recording device, a power source section for supplying driving power to said image sensing and recording device, and a switching section for controlling image sensing and recording of an object image by said image sensing and recording device are arranged on a card-like base member which can be assembled into a box by bending.

14. A camera according to claim 13, wherein said card-like base member which can be assembled into the box, has a structure constituted by slit portions and folding portions molded in advance, said slit portions being able to be separated upon assembly to form a dark box having a predetermined shape so as to oppose said optical lens to a light-receiving surface of said image sensing and recording device, and said folding portions defining portions at which said slit portions are bent.

15. A camera according to claim 12, wherein said light-receiving element array section, said analog memory section, and said transfer section are realized as a semiconductor device having an element structure stacked and integrally formed on a predetermined semiconductor substrate.

16. A camera according to claim 15, wherein said transfer section is formed as a charge transfer element group on said predetermined semiconductor substrate, said analog memory section is formed as a semiconductor memory cell group having a plurality of layers stacked on said charge transfer element group, and said light-receiving element array section is formed as a two-dimensionally arranged semiconductor light-receiving element group stacked on an uppermost layer portion of said semiconductor memory cell group having the plurality of layers.

17. A camera according to claim 16, wherein said semiconductor memory cell group is constituted by a plurality of two-dimensional analog memories stacked as layers and having signal charge storage portions respectively corresponding to the elements of said semiconductor light-receiving element group.

18. A camera according to claim 17, wherein said plurality of two-dimensional analog memories respectively include EEPROM cells.

19. A camera according to claim 15, wherein said charge transfer element group includes CCD channels each constituted by an impurity layer of a second conductivity type formed on a semiconductor substrate of a first conductivity type, and a plurality of CCDs each constituted by a transfer gate electrode and a CCD electrode embedded in an insulating layer on each of said CCD channels.

20. A camera according to claim 19, wherein each element of said semiconductor light-receiving element group includes a photodiode embedded between a layer of the second conductivity type and a layer of the first conductivity type, and a reset transistor constituted by said layer of the first conductivity type, said layer of the second conductivity type, and a gate electrode embedded in an insulating layer.

21. A camera according to claim 18, wherein said EEPROM cells have a structure constituted by layers sequentially stacked on each other in a vertical direction, each of said layers including a control gate electrode having a floating gate formed therein, source and drain regions constituted by a layer of the second conductivity type embedded in a layer of the first conductivity type, and a load resistor, and said EEPROM cells being sequentially connected to each other through wiring interlayer electrodes in the vertical direction.

22. A camera according to claim 17, wherein each of said two-dimensional analog memories includes a memory cell having an MNOS structure.

23. A camera according to claim 12, wherein said analog memory section comprises a plurality of EEPROM cells as layers integrally stacked on said transfer section constituted by said charge transfer elements, and the signal charges from said light-receiving element array section integrally stacked on said analog memory section are parallelly transferred and stored in the direction of thickness in response to a control gate pulse supplied to each of said EEPROM cells.

24. A camera according to claim 12, wherein said light-receiving element array section comprises a plurality of capacitors for respectively storing the signal charges generated by said plurality of light-receiving elements upon photoelectric conversion, said light-receiving element array section having an electronic shutter function realized by control of signal charge storage times of said capacitors.