Multiprocessor digital data processing system

• US 5,055,999 A
• Filed: 12/22/1987
• Issued: 10/08/1991
• Est. Priority Date: 12/22/1987
• Status: Expired due to Term

• Current Assignee: Life Sciences Research Partners V.Z.W., Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Kendall Square Research Corp.
• Inventors: Goodman, Nathan, Frank, Steven J., Margulies, Benson I., Weber, Frederick D., Lee, Linda O., Burkhardt, Henry III
• Primary Examiner(s): Hecker, Stuart N.
• Assistant Examiner(s): Rudolph, Rebecca L.
• Application Number:
  US07/136,930
• Time in Patent Office: 1,386 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/163
• CPC Class Codes: G06F 11/004 Error avoidance G06F11/07 and subgroups take precedence
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0766 Error or fault reporting or storing
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/1018 involving hashing techniques, e.g. inverted page tables
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 2212/272 Cache only memory architecture [COMA]
• CPC Class Codes: G06F 9/30003 Arrangements for executing specific machine instructions
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/323 for indirect branch instructions
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3856 : Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 : Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3861 : Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3865 : using deferred exception handling, e.g. exception flags
• CPC Class Codes: G06F 9/468 : Specific access rights for resources, e.g. using capability register
• CPC Class Codes: G06F 9/5016 : the resource being the memory
• CPC Class Codes: G06F 9/52 : Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: H04L 12/4637 : Interconnected ring systems
• CPC Class Codes: H04L 45/04 : Interdomain routing, e.g. hierarchical routing

Abstract

A multiprocessor digital data processing system comprises a plurality of processing cells arranged in a hierarchy of rings. The system selectively allocates storage and moves exclusive data copies from cell to cell in response to access requests generated by the cells. Routing elements are employed to selectively broadcast data access requests, updates and transfers on the rings.

Claims

1. A digital data processing apparatus comprising

A. plural memory elements for storing information-representative signals, each of at least one of which memory elements is respectively coupled to an associated central processing unit,

each said central processing unit and its respective associated memory element comprising at least part of a processing cell,

B. memory management means coupled to said plural memory elements for accessing one or more of said information-representative signals stored in said plural memory elements,

C. at least a requesting one of said central processing units including access request means for generating an access request signal representative of a request for access to an information-representative signal,

said access request means including means for generating an ownership-request signal representative of a request for priority access to an information-representative signal,

at least the memory element associated with the requesting central processing unit including control means for selectively transmitting said access-request signal to said memory management means, and

D. said memory management means including means responsive to selected ones of said ownership-request signals for

allocating, only within the memory element associated with the requesting central processing unit, physical storage space for the requested information-representative signal, wherein that space is the exclusive physical storage space for the requested information-representative signal with respect to all of said memory elements, and

storing the requested information-representative signal in that exclusive physical storage space.

2. A digital data processing apparatus according to claim 1, wherein said memory management means comprises means responsive to selected ones of said ownership-request signal for deallocating physical storage space allocated in a memory element, other than the one associated with the requesting central processing unit, for storage of the requested information-representative signal.

3. A digital data processing apparatus according to claim 2, wherein at least one said memory element includes an associated directory means for storing an SVA identifier signal uniquely identifying at least selected information-representative signals stored in that memory element.

4. A digital data processing apparatus according to claim 3, wherein

A. said access request means includes means for generating, along with said access request signal, an SVA request signal identifying the requested information-representative signal,

B. said memory management means includes interface means coupled with said directory means for comparing an SVA request signal with one or more SVA identifier signals stored in that directory means for determining whether the requested information-representative signal is stored in the memory element associated with that directory means.

5. A digital data processing apparatus according to claim 3, wherein

A. each said directory means includes one or more identifier storage locations for storing SVA identifier signals,

B. said memory management means includes means for storing in one of said identifier storage locations an SVA identifier signal associated with an information-representative signal for which physical storage space has been allocated within the associated memory element, and

C. said memory management means includes means for invalidating an SVA identifier address signal corresponding to an information-representative signal for which physical storage space has been deallocated within the associated memory element.

6. A digital data processing apparatus according to claim 1, wherein

said access request means includes means for generating a read-only request signal representative of a request for secondary access to an information-representative signal, and wherein

said memory management means includes means selectively responsive to a read-only signal generated by a requesting one of said central processing units, said read-only signal being representative of a request for secondary access to an information-representative signal stored in a memory element associated with another of said other central processing units, for transferring a copy of that information-representative signal to the memory element associated with the requesting central processing unit.

7. A digital data processing apparatus according to claim 1, wherein

said central processing units includes means for selectively generating an update signal representative of modification of an information-representative signal,

said memory management means includes means responsive to an update signal generated by an updating one of said central processing units for modifying a corresponding information-representative signal stored in the memory element associated with that central processing unit.

8. A digital data processing apparatus according to claim 7, wherein said memory management means includes means responsive to an update signal generated by said updating central processing unit, said update signal being representative of modification of a corresponding information-representative signal stored in a memory element associated with another said central processing unit, for modifying that corresponding information-representative signal.

9. A digital data processing apparatus according to claim 1, wherein

A. said access request means includes atomic-ownership means for generating an atomic-request signal representative of a request for exclusive priority access to one or more information-representative signals,

B. said memory management means includes means selectively responsive to an atomic-request signal generated by a first one of said central processing units for

i) allocating, exclusively, in the memory element associated with the first central processing unit physical storage space for said one or more requested information-representative signals and for storing those information-representative signals therein, while

ii) preventing access to any of those information-representative signals in response to a first selected access request signal generated by a second one of said central processing units.

10. A digital data processing apparatus according to claim 9, wherein said memory management means includes means for responding to a second selected access request generated by said second central Processing unit for effecting exclusive transfer of requested information-representative signals to the memory element associated with that central processing unit and for preventing access to any of those information request signals generated by the first or any other central process unit.

11. A digital data processing apparatus according to claim 9, wherein

A. said access request means further includes atomic-transaction termination means for generating a release signal representative of termination of said request for priority access to said one or more information-representative signals, and

B. said memory management means includes means responsive to said transaction-termination signal for re-enabling selective access to those information-representative signals in response to access request signals generated by any of said central processing units.

12. A digital data processing apparatus according to claim 1 comprising:

a plurality of information transfer domains each including one or more segments, said plurality of information transfer domains including a first information transfer domain having a plurality of domain(0) segments, each including an associated unidirectional bus element coupled in a ring configuration to said memory management means for transferring signals between a plurality of said processing cells.

13. A digital data processing system according to claim 12, comprising:

a domain(1) segment comprising an associated unidirectional bus element and a plurality of routing elements, each said routing element being connected to the bus element associated with the domain(1) segment and to the bus element associated with one of said domain(0) segments for transferring signals between the domain(1) segment and the associated domain(0) segment, the processing cells associated with each of said domain(0) segments being capable of information-representative signal transfer with the processing cells associated with the remainder of said domain(0) segments only through the domain(1) segment.

14. A digital data processing apparatus according to claim 1 comprising:

A. (n) information transfer domains, each respectively designated as information transfer domain(k), wherein (n) is an integer greater than or equal to two, and wherein (k) represents successive integers between (0) and (n-1), inclusive,

B. information transfer domain(0) including a plurality of domain(0) segments, each such segment including

a bus element connected to said memory management means for transferring signals between a plurality of said processing cells,

C. each information transfer domain(k), for (k) between (1) and (n-1), inclusive, including one or more corresponding domain(k) segments, wherein the number of segments in information domain(k) is less than the number of segments in domain(k-1), for each value of (k), and wherein information transfer domain(n-1) includes only one such segment.

15. A digital data processing apparatus according to claim 14 wherein each said domain(k) segment includes

A. a bus element for transferring signals within that domain(k) segment,

B. plural domain routing elements for transferring signals between that domain(k) segment and a domain(k-1) segment, each such routing element being connected for signal transfer with the respective domain(k) segment bus element and with the respective domain(k-1) segment bus element.

16. A digital data processing apparatus according to claim 15, wherein

the memory management means includes means responsive to an access-request signal directed to an information-representative signal not stored within the memory element associated with the requesting central processing unit for transmitted that access-request signal on the associated domain(0) bus element.

17. A digital data processing apparatus according to claim 16, wherein one or more said processing cells includes means for receiving an access-request signal transferred along an associated domain(0) bus for selectively generating a signal representative of the requested information-representative signal.

18. A digital data processing apparatus according to claim 16, wherein

A. each said bus element comprises a unidirectional signal flow path, and

B. said control means includes means for driving said access-request signal along the flow path defined by the associated bus element.

19. A digital data processing apparatus according to claim 16, wherein said domain routing element includes at least one of

A. means for receiving an access-request signal transferred along a bus element associated with a domain(k-1) segment, where (k) is an integer between (1) and (n-1), and for selectively transmitting a copy of that signal along the bus element associated with a corresponding domain(k) segment, and

B. means for receiving a access-request signal transferred along a bus element associated with a domain(k) segment, where (k) is an integer between (1) and (n-1), and for selectively transmitting a copy of that signal along the bus element associated with a corresponding domain(k-1) segment.

20. A digital data processing apparatus according to claim 19, wherein

A. a domain routing element connected with a domain(k) segment, where (k) is an integer between (1) and (n-1), inclusive, includes directory means for storing SVA address signals corresponding to information-representative signals stored in the plurality of memory elements contained in processing cells of domain(j) segments associated with that domain(k) segment, where (j) is an integer between (k-1) and (0), and

B. said domain routing element includes interface means coupled with said directory element and with said access request means for comparing an access-request signal with an SVA address signal to determine whether a copy of that access-request signal should be transmitted to the associated domain(k) segment.

21. In a digital data processing apparatus of the type having

plural memory elements for storing information-representative signals, each of at least one of which memory elements is respectively coupled to an associated central processing unit, each said central processing unit and its respective associated memory element comprising at least part of a processing cell, the improvement comprising

A. memory management means coupled to said plural memory elements for accessing one or more information-representative signals stored therein, and

B. said memory management means including state-defining means coupled with said plural memory elements for associating an access state with one or more information-representative signals stored therein, said access state being selected from a group of access states including one or more of

i) an exclusive owner access state associable with an information-representative signal modifiable by a central processing unit associated with a memory element in which exclusive physical storage space for that information-representative signal is allocated and in which that information-representative signal is stored, for which information-representative signal no physical storage space is allocated in any other memory element, that information-representative signal, or a copy thereof, being accessible for transfer to another memory element, and

ii) an atomic owner access state associable with an information-representative signal modifiable by a central processing unit associated with a memory element in which exclusive physical storage space for that information-representative is allocated and in which that information-representative signal is stored, for which information-representative signal no physical storage space is allocated in any other memory element, neither that information-representative signal, nor a copy thereof, being selectively accessible for transfer to any other memory element.

22. In a digital data processing apparatus according to claim 21, the further improvement in which saidstate-defining means includes means for associating with one or more information-representative signals stored in said plural memory elements an access state selected from an additional group of access states including one or more of

i) an invalid access state,

ii) a read-only access state associable with a copy of an information-representative signal subject to read-only access by a central processing unit associated with a memory element in which that only is stored, wherein said information representative signal is stored in a memory memory element element associated with another of said central processing units and is modifiable by that other central processing unit, and

iii) a nonexclusive owner access state associable with an information-representative signal modifiable by a central processing unit associated with a memory element in which that information-representative signal is stored, a copy of which information-representative signal is stored in a memory element associated with another said central processing unit.

23. In a digital data processing apparatus according to claim 22, the further improvement wherein said state-defining means includes

A. means for selectively and exclusively associating any one of

i) said atomic owner access state, and

ii) said exclusive owner access state with an information representative signal stored in said plural memory elements, and

B. means for selectively and exclusively associating said nonexclusive owner access state with one of (n) copies of an information-representative signal stored in said plural memory elements, where (n) is an integer greater than or equal to one.

24. In a digital data processing apparatus according to claim 23, the further improvement wherein said state-defining means includes means for selectively associating any one of

i) said read-only access state, and

ii) said invalid access state with (n-1) copies of an information-representative signal stored in said plural memory elements.

25. In a digital data processing apparatus according to claim 22, the further improvement wherein

A. at least a requesting one of said central processing units includes access request means for generating an access request signal representative of a request for access to an information-representative signal,

said access request means including means for generating an exclusive access request signal representative of a request for exclusive access to an information-representative signal, and

B. said state-defining means includes means responsive to an exclusive access request signal generated by said requesting central processing unit, said exclusive access request being representative of a request for exclusive access to an information-representative signal stored in a memory element associated with another of said central processing units, wherein that information-representative signal is associated with said read-only access state, for effecting exclusive transfer of that information-representative signal to said requesting central processing unit and for associating the copy of that information-representative signal stored in the memory element associated with that other central processing unit with said invalid access state.

26. In a digital data processing apparatus according to claim 21, the further improvement wherein said memory management means includes means responsive to association of said atomic access state with an information-representative signal stored in a memory element associated with a first central processing unit for preventing access to that information-representative signal in response to a first selected access request signal generated by any other said central processing unit.

27. In a digital data processing apparatus according to claim 26, the further improvement wherein

A. said memory management means includes means for responding to a second selected access request signal generated by a second central processing unit, and directed to one or more information representative signals associated with the atomic owner access state, for effecting transfer of those requested signals to the memory element associated with said second central processing unit, and

B. said state defining means includes means for associating the atomic owner state with those transferred signals for allocating, exclusively, in the memory element associated with the second central processing unit physical storage space for said one or more requested information-representative signals.

28. In a digital data processing apparatus according to claim 21, the further improvement wherein

A. said state-defining means includes means responsive to an access request signal generated by a requesting central processing unit and directed to an information-representative signal stored in a memory element associated with an owning central processing unit, said information representative signal being associated with said atomic access state, for associating with that information-representative signal a transient atomic state,

B. said owning central processing unit includes means for generating a release signal representative of a release of said requested information-representative signal from said atomic access state,

C. said memory management means includes means responsive to a release signal generated by said owning central processing unit and directed to said requested information-representative signal for transmitting a copy of that information-representative signal to the memory element associated with the requesting central processing unit.

29. In a digital data processing apparatus according to claim 22, the further improvement wherein

A. at least a requesting one of said central processing units includes access request means for generating at access request signal representative of a request for access to an information-representative signal,

said access request means includes means for generating a nonexclusive access-request signal representative of a request for nonexclusive access to an information-representative signal, and

B. said state-defining means includes means responsive to a nonexclusive access request signal generated by said requesting central processing unit, said nonexclusive access request signal being representative of a request for nonexclusive access to an information-representative signal stored in a memory element associated with another of said central processing units, wherein that information-representative signal is associated with any one of an exclusive access state and a nonexclusive access state, for effecting exclusive transfer of that information-representative signal to said requesting central processing unit and for associating the information-representative signal stored in the memory element associated with that other central processing unit with said read-only access state.

30. In a digital data processing apparatus according to claim 21, the further improvement wherein

A. at least a requesting one of said central processing units includes stop request means for generating a stop request signal representative of a pending request for atomic owner access to an information-representative signal,

B. said memory management means includes means responsive to said stop request signal for effecting exclusive storage of a next available copy of the requested information-representative signal in the memory element associated with a requesting central processing unit, and

C. said state-defining means includes means responsive to said stop request signal for assigning said atomic owner access state to said next available copy of the requested information-representative signal stored in the memory element associated with said requesting central processing unit.

31. A digital data processing apparatus according to claim 21, wherein said memory management means includes means responsive to a request for priority access to an information-representative signal generated by a first central processing unit for responding to subsequent requests for access to that same information-representative generated by others of said central processing units for generating a transient signal for transmission to said other central processing units, said transient signal being representative of current ownership of said requested information-representative signal by said first central processing unit.

50. A digital data processing according to claim 23, comprising

A. at least one said memory management means including state-defining means for associating an access state with one or more information-representative signals stored in said memory elements, said access state being selected from a group of access states including one or more of

i) an invalid access state associable with an invalid information-representative signal,

ii) a read-only access state associable with an information-representative signal subject to read-only access by a central processing unit associated with a memory element in which that information-representative signal is stored,

iii) a nonexclusive owner access state associable with an information-representative signal modifiable by a central processing unit associated with a memory element in which that information representative signal is stored, a copy of which information-representative signal is stored in a memory element associated with another said central processing unit,

iv) an exclusive owner access state associable with an information-representative signal modifiable by a central processing unit associated with a memory element in which that information-representative signal is stored, no copy of which information-representative signal is stored in a memory element associated with another said central processing unit, that information-representative signal, or a copy thereof, being accessible for transfer to a memory element associated with another said central processing unit, and

v) an atomic owner access state associable with an information-representative signal modifiable by a central processing unit associated with a memory element in which that information-representative signal is stored, no copy of which information-representative signal is stored in a memory element associated with another said central processing unit, neither that information-representative signal, nor a copy thereof, being selectively accessible for transfer to a memory element associated with another said central processing unit.

51. In a digital data processing apparatus according to claim 50, the further improvement wherein said state-defining means includes

A. means for selectively and exclusively associating any one of

i) said atomic owner access state, and

ii) said exclusive owner access state with an information-representative signal stored in said plural memory elements, and

B. means for selectively and exclusively associating said non-exclusive owner access state with one of (n) copies of an information-representative signal stored in said plural memory elements, where (n) is an integer greater than or equal to one.

52. In a digital data processing apparatus according to claim 51, the further improvement wherein said state-defining means includes means for selectively associating any one of

i) said read-only access state, and

ii) said invalid access state with (n-1) copies of an information-representative signal stored in said plural memory elements.

53. In a digital data processing apparatus according to claim 50, the further improvement wherein at least one said memory management means includes means responsive to association of said atomic access state with an information-representative signal stored in a memory element associated with a first central processing unit for preventing access to that information-representative signal in response to a first selected access request signal generated by any other said central processing unit.

54. A digital data processing apparatus according to claim 53, wherein

A. at least one said memory management means includes means for responding to a second selected access request signal generated by a second central processing unit, and directed to one or more information representative signals associated with the atomic owner access state, for effecting transfer of those requested signals to the memory element associated with said second central processing unit, and

B. said state-defining means includes means for associating the atomic owner state with those transferred signals for allocating, exclusively, in the memory element associated with the second central processing unit physical storage space for said one or more requested information-representative signals.

55. A digital data processing apparatus according to claim 50, wherein

A. said state-defining means includes means responsive to an access request signal generated by a requesting central processing unit and directed to an information-representative signal stored in a memory element associated with an owning central processing unit, said information-representative signal being associated with said atomic access state, for associating with that information-representative signal a transient atomic state,

B. said owning central processing unit includes means for generating a release signal representative of a release of said requested information-representative signal from said atomic access state,

C. said memory management means includes means responsive to a release signal generated by said owning central processing unit and directed to said requested information-representative signal for transmitting a copy of that information-representative signal to the memory element associated with the requesting central processing unit.

56. In a digital data processing apparatus according to claim 50, the further improvement wherein

A. at least a requesting one of said central processing units includes access request means for generating an access request signal representative of a request for access to an information-representative signal,

said access request means including means for generating an exclusive access request signal representative of a request for exclusive access to an information-representative signal, and

B. said state-defining means includes means responsive to an exclusive access request signal generated by said requesting central processing unit, said exclusive access request being representative of a request for exclusive access to an information-representative signal stored in a memory element associated with another of said central processing units, wherein that information-representative signal is associated with said read-only access state, for effecting exclusive transfer of that information-representative signal to said requesting central processing unit and for associating the copy of that information-representative signal stored in the memory element associated with that other central processing unit with said invalid access state.

57. In a digital data processing apparatus according to claim 50, the further improvement wherein

A. at least a requesting one of said central processing units includes access request means for generating an access request signal representative of a request for access to an information-representative signal,

said access request means includes means for generating a nonexclusive access-request signal representative of a request for nonexclusive access to an information-representative signal, and

B. said state-defining means includes means responsive to a nonexclusive access request signal generated by said requesting central processing unit, said nonexclusive access request signal being representative of a request for nonexclusive access to an information-representative signal stored in a memory element associated with another of said central processing units, wherein that information-representative signal is associated with any one of an exclusive access state and a nonexclusive access state, for effecting exclusive transfer of that information-representative signal to said requesting central processing unit and for associating the information-representative signal stored in the memory element associated with that other central processing unit with said read-only access state.

58. In a digital data processing apparatus according to claim 50, the further improvement wherein

A. at least a requesting one of said central processing units includes stop request means for generating a stop request signal representative of a pending request for atomic owner access to an information-representatives signal,

B. said memory management means includes means responsive to said stop request signal for effecting exclusive storage of a next available copy of the requested information-representatives signal in the memory element associated with a requesting central processing unit, and

C. said state-defining means includes means responsive to said stop request signal for assigning said atomic owner access state to said next available copy of the requested information-representative signal stored in the memory element associated with said requesting central processing unit.

59. A digital data processing apparatus according to claim 50, wherein said memory management means includes means responsive to a request for priority access to an information-representative signal generated by a first central processing unit for responding to subsequent requests for access to that same information-representative generated by others of said central processing units for generating a transient signal for transmission to said other central processing units, said transient signal being representative of current ownership of said requested information-representative signal by said first central processing unit.

32. A digital data processing apparatus comprising

a plurality of information transfer domains each including one or more segments,

said plurality of information transfer domains including a first information transfer domain having a plurality of domain(0) segments, each, including an associated bus element and a plurality of processing cells connected to said bus element for transferring signals therebetween,

each of said processing cells including a central processing unit coupled to an associated content-addressable memory element for storing information-representative signals, each said information-representative signal being identifiable by a corresponding SVA identifier,

at least a requesting one of said processing cells including means for generating an access-request signal including an identifier component representative of an SVA identifier of an information-representative signal stored in a memory element of any other of said processing cells, said requesting processing cell including means for transmitting that access-request signal on the associated domain(0) bus element,

said plurality of information transfer domains further including a second information transfer domain having a domain(1) segment comprising an associated unidirectional bus element and a plurality of routing elements, each said routing element being connected to the bus element associated with the domain(1) segment and to the bus element associated with one of said domain(0) segments for transferring signals therebetween,

each said routing element including directory means for storing SVA identifier signals of information-representative signals stored in memory elements of the processing cells of the associated domain(0) segment, and

each said routing element further including means for receiving an access-request signal transferred along any one of the bus element of the domain(1) segment and the bus element of the associated domain(0) segment and for selectively transmitting a copy of that access-request signal along the bus element associated with the other of those bus elements based on a comparison of the identifier component of that access-request signalwith said SVA identifier signals in said directory element.

33. A digital data processing apparatus comprising

A. (n) information transfer domains, each respectively designated as information transfer domain(k), wherein (n) is an integer greater than or equal to two, and wherein (k) represents successive integers between (0) and (n-1), inclusive,

B. information transfer domain(0) including a plurality of domain(0) segments, each such segment including

i) a plurality of processing cells, each processing cell including a central processing unit connected to signal transfer with an associated content-addressable memory element for storing information-representative signals, each said information-representative signal being identifiable by a corresponding SVA identifier, each said processing cell further including memory management means for accessing information-representative signals stored in that content addressable memory element,

ii) a bus element connected to those plural memory management means for transferring signals between the processing cells of that domain(0) segment,

iii) the memory management means of at least a requesting one of said processing cells including means for generating an access-request signal including an identifier component representative of an SVA identifier of an information-representative signal stored in a memory element of any other of said processing cells,

said memory management means further including means for transmitting that access request signal on the bus element of the domain(0) segment with which the requesting processing cell is associated,

C. each information transfer domain(k), wherein (k) represents successive integers between (1) and (n-1), inclusive, including one or more corresponding domain(k) segments, wherein the number of segments in information domain(k) is less than the number of segments in domain(k-1), for each value of (k), and wherein information transfer domain(n-1) includes only one such segment, each domain(k) segment including

i) a bus element for transferring signals within that domain(k) segment,

ii) plural domain routing elements for transferring signals between that domain(k) segment and a domain(k-1) segment, each such routing element being connected for signal transfer with the respective domain(k) segment bus element and with respective domain(k-1) segment bus element,

each said domain routing element including directory means for storing SVA identifier signals corresponding to information-representative signals stored in the plurality ofmemory elements contained in processing cells of domain(j) segments associated with that domain(k) segment, where (j) is an integer between (k-1) and (0), and

each said domain routing element further including means for receiving an access-request signal transferred along any one of the bus element of the domain(k) segment with which it is connected and the domain(k-1) segment with which it is connected, for selectively transmitting a copy of that access-request signal along the bus element of the other of those segments based on a comparison of the identifier component of that access-request signal with the SVA identifier signals in said directory element.

34. A digital data processing apparatus according to claim 33, wherein

A. at least a requesting one of said central processing units includes access-request means for generating an access-request signal representative of a request for access to an information-representative signal stored in any one of said memory elements,

B. the memory management means associated with the requesting central processing unit includes control means responsive to an access-request signal directed to an information-representative signal not stored within the associated memory element for transmitting that signal on the associated domain(0) bus element.

35. A digital data processing apparatus according to claim 34, wherein one or more said processing cells includes means for receiving an access-request signal transferred along an associated domain(0) bus for selectively generating a signal representative of the requested information-representative signal.

36. A digital data processing apparatus according to claim 34, wherein

A. each such bus element comprises a unidirectional information-representative signal flow path, and

B. said control means includes means for driving said access-request signal along the flow path defined by the associated bus element.

37. A digital data processing apparatus according to claim 34, wherein said domain routing element includes at least one of

A. means for receiving an access-request signal transferred along a bus element associated with a domain(k-1) segment, where (k) is an integer between (1) and (n-1), and for selectively transmitting a copy of that signal along the bus element associated with a corresponding domain(k) segment, and

B. means for receiving an access-request signal transferred along a bus element associated with a domain(k) segment, where (k) is an integer between (1) and (n-1), and for selectively transmitting a copy of that signal along the bus element associated with a corresponding domain(k-1) segment.

38. A digital data processing apparatus according to claim 37, wherein

A. a domain routing element connected with a domain(k) segment, where (k) is an integer between (1) and (n-1), inclusive, includes directory means for storing SA address signals corresponding to information-representative signals stored in the plurality of memory elements contained in processing cells of domain(j) segments associated with that domain(k) segment, where (j) is an integer between (k-1) and (0), and

B. said domain routing element includes interface means coupled with said directory element and with said access request means for comparing an access-request signal with an SA address signal to determine whether a copy of that access-request signal should be transmitted to the associated domain(k) segment.

39. A digital data processing apparatus according to claim 33 wherein

A. at least a requesting one of said central processing units includes access request means for generating an access request signal representative of a request for access to an information-representative signal,

said access request means including means for generating an ownership-request signal representative of a request for priority access to an information-representative signal,

B. at least one said memory management means includes means responsive to selected ones of said ownership request signals for allocating, exclusively, within the memory element associated with the requesting central processing unit, physical storage space for the requested information-representative signal and for storing that signal therein.

40. A digital data processing apparatus according to claim 39, wherein at least one said memory management means comprises means responsive to selected ones of said ownership-request signal for deallocating physical storage space allocated in a memory element, other than the one associated with the requesting central processing unit, for storage of the requested information-representative signal.

41. A digital data processing apparatus according to claim 40, wherein at least one said memory management means includes an associated directory means for storing an SA address signal uniquely identifying at least selected information-representative signals stored in the associated memory element.

42. A digital data processing apparatus according to claim 41, wherein

A. said access request means includes means for generating, along with said access request signal, an SA request signal identifying the requested information-representative signal,

B. said at least one memory management means includes interface means coupled with said directory means for comparing an SA request signal with one or more SA address signals stored in that directory means for determining whether the requested information-representative signal is stored in the memory element associated with that directory means.

43. A digital data processing apparatus according to claim 41, wherein

A. each said director means includes one or more address storage locations for storing SA address signals,

B. said at least one memory management means includes means for storing in one of said address storage locations an SA address signal associated with an information-representative signal for which physical storage space has been allocated within the associated memory element, and

C. said at least one memory management means includes means for invalidating an SA address signal corresponding to an information-representative signal for which physical storage space has been deallocated within the associated memory element.

44. A digital data processing apparatus according to claim 39, wherein

said access request means includes means for generating a read-only request signal representative of a request for secondary access to an information-representative signal, and wherein

at least one said memory management means includes means selectively responsive to a read-only signal generated by a requesting one of said central processing units, said read-only signal being representative of a request for secondary access to an information-representative signal stored in a memory element associated with another of said other central processing units, for transferring a copy of that information-representative signal to the memory element associated with the requesting central processing unit.

45. A digital data processing apparatus according to claim 39, wherein

said central processing units includes means for selectively generating an update signal representative of modification of an information-representative signal,

at least one said memory management means includes means responsive to an update signal generated by an updating one of said central processing units for modifying a corresponding information representative signal stored in the memory element associated wit that central processing unit.

46. A digital data processing apparatus according to claim 45, wherein at least one said memory management means includes means responsive to an update signal generated by said updating central processing unit, said update signal being representative of modification of a corresponding information representative signal stored in a memory element associated with another said central processing unit, for modifying that corresponding information-representative signal.

47. A digital data processing apparatus according to claim 39, wherein

A. said access request means includes atomic-ownership means for generating an atomic-request signal representative of a request for exclusive priority access to one or more information-representative signals,

B. said memory management means includes means selectively responsive to an atomic-request signal generated by a first one of said central processing units for

i) allocating, exclusively, in the memory element associated with the first central processing unit physical storage space for said one or more requested information-representative signals and for storing those information-representative signals therein, while

ii) preventing access to any of those information-representative signals in response to a first selected access request signal generated by a second one of said central processing units.

48. A digital data processing apparatus according to claim 47, wherein said memory management means includes means for responding to a second selected access request generated for said second central processing unit for effecting exclusive transfer of requested information-representative signals to the memory element associated with that central processing unit and for preventing access to any of those information request signals generated by the first or any other central process unit.

49. A digital data processing apparatus according to claim 47, wherein

A. said access request means further includes atomic-transaction termination means for generating a release signal representative of termination of said request for priority access to said one or more information-representative signals, and

B. said memory management means includes means responsive to said transaction-termination signal for re-enabling selective access to those information-representative signals in response to access request signals generated by any of said central processing units.

60. A digital data processing apparatus comprising

A. a plurality of memory elements for storing information-representative signals, each of at least one of which memory elements is respectively coupled to an associated central processing unit,

each said central processing unit and its respective associated memory element comprising at least part of a processing cell,

at least one of said processing cells being a remote processing cell,

B. bus means for transmitting signals between said memory elements,

C. remote interface means coupled to said remote cell for transferring signals between the associated memory element and the bus means, and

D. memory management means coupled to said memory elements for accessing information-representative signals stored therein,

each said central processing unit including control means for selectively transmitting said access-request signal to said memory management means,

said memory management means including means responsive to selected ones of said ownership-request signals for

allocating, only within the memory element associated with the requesting central processing unit, physical storage space for the requested information-representative signal, wherein that space is the exclusive physical storage space for the requested information-representative signal with respect to all of said memory elements, and

storing the requested information-representative signal in that exclusive physical storage space.

61. A digital data processing apparatus according to claim 60, wherein said memory management means includes

means for deallocating physical storage space if any, allocated to the requested information-representative signal within the memory elements associated with said central processing units other than the requesting one.

62. A digital data processing apparatus according to claim 61, wherein

said remote cell resides at a point physically remote from said bus means, and wherein

said interface means includes means for transmitting said information-representative signal between said physically remote point and said bus means.

63. A digital data processing apparatus according to claim 62, wherein said remote interface means includes fiber optic transmission media for carrying signals between said remote cell and said bus means.

64. A method of operating a digital data processing apparatus, said apparatus including a plural memory elements for storing information-representative signals, each of at least one of which memory elements is respectively coupled to an associated central processing unit, each said central processing unit and its respective associated memory element comprising at least part of a processing cell, the method comprising the steps of

A. generating within a requesting one of said central processing units an ownership-request signal representative of a request for priority access to an information-representative signal,

B. determining whether the requested information-representative signal is stored within a memory element other than one associated with the requesting central processing unit, and

C. responding to a determination that the requested information-representative signal is stored in a memory element other than the one associated with the requesting central processing unit for

allocating, only within the memory element associated with the requesting central processing unit, physical storage space for the information-representative signal, wherein that space is the exclusive storage space for the requested information-representative signal with respect to all of said memory elements, and

storing the requested information-representative signal in that exclusive physical storage space.

65. A method of operating a digital data processing apparatus according to claim 64, wherein said responding step includes the further step of

deallocating physical storage space, if any, allocated to the requested information-representative signal within the memory elements associated with central processing units other than the requesting one.

66. In a method for operating a digital data processing apparatus of the type having

plural memory elements for storing information-representative signals, each of at least one of which memory elements is respectively coupled to an associated central processing unit, each said central processing unit and its respective associated memory element comprising at least part of a processing cell, the improvement comprising the steps of

A. associating an access state with one or more information-representative signals stored in said plural memory elements, said access state being selected from a group of access states including one or more of

i) an exclusive owner access state associable with an information-representative signal modifiable by a central processing unit associated with a memory element in which exclusive physical storage space for that information-representative is allocated and in which that information-representative signal is stored, for which information-representative signal no physical storage space is allocated in any other memory element, that information-representative signal, or a copy thereof, being accessible for transfer to another memory element, and

ii) an atomic owner access state associable with an information-representative signal modifiable by a central processing unit associated with a memory element in which exclusive physical storage space for that information-representative is allocated and in which that information-representative signal is stored, for which information-representative signal no physical storage space is allocated in any other memory element, neither that information-representative signal, nor a copy thereof, being selectively accessible for transfer to any other memory element.

67. In a method according to claim 66, the further improvement in which said access state-associating step includes the step of associating with one or more information-representative signals stored in said plural memory elements an access state selected from a group of access states including

i) invalid access state,

ii) a read-only access state associable with a copy of an information-representative signal subject to read-only access by a central processing unit associated with a memory element in which that copy is stored, wherein said information representative signal is stored in a memory element associated with another of said central processing units and is modifiable by that other central processing unit, and

iii) a nonexclusive owner access state associable with an information-representative signal modifiable by a central processing unit associated with a memory element in which that information-representative signal is stored, a copy of which information-representative signal is stored in a memory element associated with another said central processing unit.

68. In a method for operating a digital data processing apparatus according to claim 66, the further improvement comprising the steps of

A. generating, within a requesting one of said central processing units, an exclusive access request signal representative of a request for priority access to an information-representative signal, and

B. responding to an exclusive access request signal generated by said requesting central processing unit, said exclusive access request being representative of a request for exclusive access to an information-representative signal stored in a memory element associated another of said central processing units, wherein that information-representative signal is associated with an access state other than said atomic ownership state, for effecting exclusive transfer of that information-representative signal to said requesting central processing unit and for associating the copy of that information-representative signal stored in the memory element associated with that other central processing unit with the invalid access state.