Analog hardware for learning neural networks

• US 5,056,037 A
• Filed: 12/28/1989
• Issued: 10/08/1991
• Est. Priority Date: 12/28/1989
• Status: Expired due to Fees

• Current Assignee: The United States of America As Represented By The Secretary of Agriculture
• Original Assignee: United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration
• Inventors: Eberhardt, Silvio P.
• Primary Examiner(s): MacDonald, Allen R.
• Assistant Examiner(s): Davis, George
• Application Number:
  US07/463,720
• Time in Patent Office: 649 Days
• Field of Search: 364/513, 364/807, 364/131, 365/117
• US Class Current: 706/39
• CPC Class Codes: G06N 3/065 Analogue means

Abstract

This is a recurrent or feedforward analog neural network processor having a multi-level neuron array and a synaptic matrix for storing weighted analog values of synaptic connection strengths which is characterized by temporarily changing one connection strength at a time to determine its effect on system output relative to the desired target. That connection strength is then adjusted based on the effect, whereby the processor is taught the correct response to training examples connection by connection.

Claims

1. A neural network processor capable of fully-parallel analog implementation of both single-attractor and multiple-attractor configurations with maximum speed of operation comprising:

a) a plurality of input neurons each having an input for receiving a voltage stimulus and an output for outputting a voltage output;

b) a plurality of output neurons each having an input for receiving a voltage input and an output for outputting a voltage output;

c) a synaptic array comprising a plurality of synapses connecting said output of respective ones of said input neurons to said input of respective ones of said output neurons, each of said synapses having a weighting factor associated therewith determining a conductance value therethrough and means for changing said weighting factor including a weighting factor input;

d) a weighting factor update conductor disposed throughout said synaptic array;

e) a plurality of individually addressable switches connected between said weighting factor input of respective ones of said synapses and said weighting factor update conductor;

f) learning controller means connected to said individually addressable switches and said weighting factor update conductor for enabling selected ones of said switches to connect said weighting factor input of a corresponding one of said synapses to said weighting factor update conductor and for simultaneously applying a weighting factor update voltage value to said weighting factor update conductor; and

,

wherein said learning controller means includes logic for updating each said synapse in turn by enabling a corresponding one of said individually addressable switches, making an initial change in the conductance value of said corresponding synapse, evaluating corresponding changes at outputs of said output neurons, and implementing therefrom a learning rule to determine a final change in said conductance of said corresponding synapse.

2. The neural network processor of claim 1 wherein said learning rule determines said final change in the conductance value of said corresponding synapse as:

##EQU3## where Δ

w is the final change in the conductance value of said corresponding synapse, η

is a previously-established learning rate, o⁺ and o^- are, respectively, values of the output of an i^th one of said output neurons before and after said learning controller means makes said initial change, t_i is a target value for the output of the i^th one of said output neurons, and "sign" is a direction in which the output of the i^th output neuron changes with respect to t_i.

3. The neural network processor of claim 1 wherein said learning controller means comprises:

a) a plurality of learning rule processor means connected to said output of respective ones of said output neurons for determining an error reduction or increase due to a change in the output of each of said output neurons in response to voltage stimuli applied to said inputs of said input neurons and said initial change in the conductance value of said corresponding synapse, according to a learning rule implemented thereby;

b) summing amplifier means for receiving said component of error from said plurality of learning rule processor means at an input thereof and for providing a summation thereof at an output;

c) scaling means for receiving said summation from said summing amplifier means at an input thereof and for providing said summation scaled by a pre-established learning rate at an output thereof;

d) update generator means for receiving a scaled summation from said scaling means at an input thereof and for generating a voltage signal required to change the conductance of a said synapse and applying said voltage signal to said weighting factor update conductor; and

,

e) digital events sequencer means having a CLOCK input thereto for causing said digital event sequencer means to repeatedly sequence through a plurality of learning steps.

4. The neural network processor of claim 3 wherein said learning rule determines said final change in the conductance value of said corresponding synapse as:

##EQU4## where Δ

w is the final change in the conductance value of said corresponding synapse, η

is a previously-established learning rate, o⁺ and o^- are, respectively, values of the output of an i^th one of said output neurons before and after said learning controller means makes said initial change, t_i is a target value for the output of the i^th one of said output neurons, and "sign" is a direction in which the output of the i^th output neuron changes with respect to t_i.

5. A neural network processor capable of fully-parallel analog implementation of both single-attractor and multiple-attractor configurations with maximum speed of operation comprising:

a) a data retrieval network portion comprising,

a1) a plurality of input neurons each having an input for receiving a voltage stimulus and an output for outputting a voltage output,

a2) a plurality of output neurons each having an input for receiving a voltage input and an output for outputting a voltage output, and

a3) a synaptic array comprising a plurality of synapses connecting said output of respective ones of said input neurons to said input of respective ones of said output neurons, each of said synapses having a weighting factor associated therewith determining a conductance value therethrough and means for changing said weighting factor including a weighting factor input; and

,

b) a learning network portion comprising,

b1) a weighting factor update conductor disposed throughout said synaptic array,

b2) a plurality of individually addressable switches connected between said weighting factor input of respective ones of said synapses and said weighting factor update conductor, and

b3) learning controller means connected to said individually addressable switches and said weighting factor update conductor for enabling selected ones of said individually addressable switches to connect said weighting factor input of a corresponding one of said synapses to said weighting factor update conductor and for simultaneously applying a weighting factor update voltage value to said weighting factor update conductor, wherein said learning controller means includes logic for updating each said synapse in turn by enabling a corresponding one of said individually addressable switches, making an initial change in the conductance value of said corresponding synapse, directly evaluating corresponding changes at outputs of said output neurons, and implementing therefrom a learning rule to determine a final change in said conductance of said corresponding synapse.

6. The neural network processor of claim 5 wherein said learning rule determines said final change in the conductance value of said corresponding synapse as:

##EQU5## where Δ

w is the final change in the conductance value of said corresponding synapse, η

is a previously-established learning rate, o⁺ and o^- are, respectively, values of the output of an i^th one of said output neurons before and after said learning controller means makes said initial change, t_i is a target value for the output of the i^th one of said output neurons, and "sign" is a direction in which the output of the i^th output neuron changes with respect to t_i.

7. The neural network processor of claim 5 wherein said learning controller means comprises:

a) a plurality of learning rule processor means connected to said output of respective ones of said output neurons for determining an error reduction or increase due to a change in the output of each of said output neurons in response to voltage stimuli applied to said inputs of said input neurons and said initial change in the conductance value of said corresponding synapse, according to a learning rule implemented thereby;

b) summing amplifier means for receiving said component of error from said plurality of learning rule processor means at an input thereof and for providing a summation thereof at an output;

c) scaling means for receiving said summation from said summing amplifier means at an input thereof and for providing said summation scaled by a pre-established learning rate at an output thereof;

d) update generator means for receiving a scaled summation from said scaling means at an input thereof and for generating a voltage signal required to change the conductance of a said synapse and applying said voltage signal to said weighting factor update conductor; and

,

e) digital events sequencer means having a CLOCK input thereto for causing said digital event sequencer means to repeatedly sequence through a plurality of learning steps.

8. The neural network processor of claim 7 wherein said learning rule determines said final change in the conductance value of said corresponding synapse as:

##EQU6## where Δ

w is the final change in the conductance value of said corresponding synapse, η

is a previously-established learning rate, o⁺ and o^- are, respectively, values of the output of an i^th one of said output neurons before and after said learning controller means makes said initial change, t_i is a target value for the output of the i^th one of said output neurons, and "sign" is a direction in which the output of the i^th output neuron changes with respect to t_i.

9. A neural network processor capable of fully-parallel analog implementation of both single-attractor and multiple-attractor configurations with maximum speed of operation comprising:

a) a data retrieval network portion comprising,

a1) a plurality of input neurons each having an input for receiving a voltage stimulus and an output for outputting a voltage output,

a2) a plurality of output neurons each having an input for receiving a voltage input and an output for outputting a voltage output, and

a3) a synaptic array comprising a plurality of synapses connecting said output of respective ones of said input neurons to said input of respective ones of said output neurons, each of said synapses having a weighting factor associated therewith determining a conductance valve therethrough and means for changing said weighting factor including a weighting factor input;

b) a learning network portion comprising,

b1) a weighting factor update conductor disposed throughout said synaptic array,

b2) a plurality of individually addressable switches connected between said weighting factor input of respective ones of said synapses and said weighting factor update conductor, and

b3) learning controller means connected to said individually addressable switches and said weighting factor update conductor for enabling selected ones of said individually addressable switches to connect said weighting factor input of a corresponding one of said synapses to said weighting factor update conductor and for simultaneously applying a weighting factor update voltage value to said weighting factor update conductor, said learning controller means comprising,

a plurality of learning rule processor means connected to said output of respective ones of said output neurons for determining an error reduction or increase due to a change in the output of each of said output neurons in response to voltage stimuli applied to said inputs of said input neurons and said initial change in the conductance value of said corresponding synapse, according to a learning rule implemented thereby,

summing amplifier means for receiving said component of error from said plurality of learning rule processor means at an input thereof and for providing a summation thereof at an output,

scaling means for receiving said summation from said summing amplifier means at an input thereof and for providing said summation scaled by a pre-established learning rate at an output thereof,

update generator means for receiving a scaled summation from said scaling means at an input thereof and for generating a voltage signal required to change the conductance of a said synapse and applying said voltage signal to said weighting factor update conductor, and,

digital events sequencer means having a CLOCK input thereto for causing said digital event sequencer means to repeatedly sequence through a plurality of learning steps.

10. The neural network processor of claim 9 wherein said learning rule determines said final change in the conductance value of said corresponding synapse as:

##EQU7## where Δ

w is the final change in the conductance value of said corresponding synapse, η

is a previously-established learning rate, o⁺ and o^- are, respectively, values of the output of an i^th one of said output neurons before and after said learning controller means makes said initial change, t_i is a target value for the output of the i^th one of said output neurons, and "sign" is a direction in which the output of the i^th output neuron changes with respect to t_i.