Memory device

• US 5,056,089 A
• Filed: 02/06/1989
• Issued: 10/08/1991
• Est. Priority Date: 02/08/1988
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Yamaguchi, Atsuo, Takahira, Kenichi, Fujioka, Shuzo, Matsubara, Toshiyuki, Inoue, Takesi, Furuta, Shigeru
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): CHUNG, PHUNG M
• Application Number:
  US07/306,565
• Time in Patent Office: 974 Days
• Field of Search: 371/3, 371/15.1, 371/22.4, 371/27, 371/22.3, 371/21.1
• US Class Current: 714/703
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/2215 to test error correction or detection circuits

Abstract

A memory system storing data detects and corrects an error in the stored data. The memory device includes a coding circuit for generating a systematic code including a data word and an error checking and correcting (ECC) code when the data word is supplied from a data bus during data writing, a memory cell array for storing the systematic code, and a sense amplifier for reading the systematic code from the memory cell. An error checking and correcting system generates a syndrome from the systematic code, decodes the syndrome to determine whether an error exists, identifies a bit position at which an error has occurred, and corrects the error contained in the data word by inverting a bit of the data word in the position at which the error has occured. The system includes a multiplexer for outputting the corrected data word to the data bus and a code reading circuit, for example, an ECC code register, for reading the ECC code generated by the coding circuit directly into the data bus. With this arrangement, it is possible to immediately and independently check the function of the coding circuit without influence from the memory cell array.

Claims

1. A memory system for storing data and detecting and correcting an error in the stored data comprising:

an error checking and correcting (ECC) code generating circuit having an input connected to a data bus for generating an error checking and correcting code in response to a data word supplied from the data bus during data writing, said ECC code generating circuit having an output from which the ECC code is output, the data word and the ECC code together constituting a systematic code;

a memory device having a first input connected to the data bus to receive the data word and a second input connected to the output of said ECC code generating circuit for receiving and storing the systematic code and having an output;

an error detecting and correcting system connected to the output of said memory device for reading the systematic code, calculating a syndrome from the systematic code read from said memory device, decoding the syndrome to determine whether an error exists in a bit in the data word and to identify a bit position at which an error has occurred, and correcting the error contained in the data word by inverting the bit of the data word at the bit position at which the error was identified;

output means for outputting the corrected data word from the error detecting and correcting system to said data bus; and

code reading means for reading out the ECC code generated by said ECC code generating circuit directly into said data bus whereby functional checking of said code generating circuit can be immediately performed without being influenced by said memory device.

2. The memory system according to claim 1 wherein said code reading means includes a register having an input connected to the output of said ECC code generating circuit and an output connected to said data bus for holding the ECC code generated by said ECC code generating circuit and outputting the ECC code to said data bus.

3. The memory system according to claim 2 wherein said error detecting and correcting system includes a circuit for selectively supplying the data word read from said memory device to the input of said ECC code generating circuit, for regenerating the ECC code corresponding to the data word read from said memory device by said ECC code generating circuit, and for applying an exclusive-OR function to the regenerated ECC code and the ECC code read from said memory device, thereby generating a syndrome.

4. The memory system according to claim 2 wherein said register is a linear feedback shift register (LFSR) for controlling said memory device to sequentially input a plurality of test patterns to said ECC code generating circuit, to compress the ECC code output from said ECC code generating circuit in accordance with the test patterns, and to check said ECC code generating circuit on the basis of the result.

5. The memory system according to claim 1 wherein said code reading means includes:

a data latch circuit having an input connected to said data bus and an output connected to the input of said ECC code generating circuit for holding a data word written from said data bus and inputting the data word into said ECC code generating circuit; and

a multiplexer connected between the output of said ECC code generating circuit and said data bus for selectively outputting the ECC code generating by said ECC code generating circuit to said data bus.

6. The memory system according to claim 5 wherein said error detecting and correcting system includes a circuit for selectively supplying the data word read from said memory device to the input of said ECC code generating circuit, for regenerating the ECC code corresponding to the data word read from said memory device by said ECC code generating circuit, and for applying an exclusive-OR function to the regenerated ECC code and the ECC code read from said memory device, thereby generating a syndrome.

7. A memory system for storing data received over a data bus and for detecting and correcting errors in the stored data comprising:

a first error checking and correcting (ECC) code generating circuit having an input connected to a data bus for receiving a data word to be stored and an output for outputting a first ECC code corresponding to the data word, the data word and the first ECC code together constituting a systematic code;

a memory device having a first input connected to the data bus to receive the data word and a second input connected to the output of said first ECC code generating circuit for receiving and storing the systematic code, said memory device having an output for outputting the stored systematic code;

a syndrome generating a circuit having an input connected to the output of said memory device for receiving the stored systematic code from said memory device and having an output for generating a syndrome which indicates whether an error is present in a bit in the stored data word and outputting the syndrome at the output;

a syndrome decoder having an input connected to the output of said syndrome generating circuit for receiving the syndrome and decoding the syndrome to identify a bit position of the data word at which an error has occurred and having an output for outputting a decoded word identifying the bit position at which an error was identified;

a bit correcting circuit having a first input connected to the output of said syndrome decoder for receiving the decoded word and a second input connected to the output of said memory device for receiving the stored data word and inverting the bit of the stored data word corresponding to the identified bit position, thereby correcting the error;

a multiplexer having a plurality of input including a first input connected to the output of said syndrome generating circuit and a second input connected to the output of said bit correcting circuit and having a first output of connected to the data bus for selectively enabling one of the first and second inputs to be output from said memory system; and

means for outputting the first ECC code from the output of said first ECC code generating circuit to the data bus separately from the first ECC code of the systematic code stored in said memory device.

8. A memory system according to claim 7 wherein said means for outputting includes an ECC code register having an input connected to the output of said first ECC code generating circuit and an output connected to said data bus.

9. A memory system according to claim 7 wherein said means for outputting comprises a third input of said multiplexer connected to the output of said first ECC code generating circuit and a second output of said multiplexer connected to the data bus for outputting to the data bus the first ECC code from the output of said first ECC code generating circuit.

10. A memory system according to claim 9 comprising a data latch having an input connected to the data bus and an output connected to the input of said first ECC code generating circuit and to the first input of said memory device.

11. A memory system according to claim 7 wherein said syndrome generating circuit includes (i) a second ECC code generating circuit having an input connected to the output of said memory device for receiving the stored data word of the systematic code from said memory device and an output for outputting a second ECC code corresponding to the stored data word and (ii) an EXCLUSIVE-OR device having a first input connected to the output of the first ECC code generating circuit for receiving the first ECC code, a second input connected to the output of the second ECC code generating circuit for receiving the second ECC code, and an output for outputting an EXCLUSIVE-OR function of the first and second ECC codes as the syndrome.

12. A memory system according to claim 7 comprising:

a first switch having a first fixed contact connected to the data bus, a second fixed contact connected to the output of said memory device for receiving the stored data word, and a movable contact connected to the input of said first ECC code generating circuit;

a second switch having a movable contact connected to the output of first ECC code generating circuit, a first fixed contact connected to the input of said memory device, and a second fixed contact; and

an EXCLUSIVE-OR device having a first input connected to the output of said memory device for receiving the stored ECC code, a second input connected to the second fixed contact of said second switch, and an output, wherein, when the movable and first fixed contacts of said first switch are electrically connected to each other and the movable and first fixed contacts of said second switch are electrically connected to each other, the data word from the data bus and the first ECC code generated for the data word by said first ECC code generating circuit are written into said memory device and wherein, when the movable and second fixed contacts of said first switch are electrically connected to each other and the movable and second fixed contacts of said second switch are electrically connected to each other, said syndrome generating circuit comprises said first ECC code generating circuit and said EXCLUSIVE-OR device, the systematic code is read from said memory device, whereby errors in the data word of the systematic code are detected and corrected and the corrected data word is output to the data bus.