Recognition procedure and an apparatus for carrying out the recognition procedure

• US 5,056,147 A
• Filed: 05/09/1990
• Issued: 10/08/1991
• Est. Priority Date: 05/16/1989
• Status: Expired due to Fees

• Current Assignee: Products From Ideas Limited
• Original Assignee: Products From Ideas Limited
• Inventors: Turner, Stephen J., Lilley, John B.
• Primary Examiner(s): Boudreau, Leo H.
• Application Number:
  US07/520,195
• Time in Patent Office: 517 Days
• Field of Search: 382/18, 382/20, 382/49, 382/42, 382/14
• US Class Current: 382/159
• CPC Class Codes: G06F 7/023 adaptive, e.g. self learning
• CPC Class Codes: G06Q 20/341 Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
• CPC Class Codes: G06Q 20/40145 Biometric identity checks
• CPC Class Codes: G07C 9/257 electronically G07C9/26 takes precedence
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system

Abstract

Apparatus and methods are disclosed for recognizing patterns, i.e., comparing a stored pattern with a pattern to be measured. The apparatus is taught a stored or reference pattern by assigning a first binary value to each of a plurality of addressable data stores at locations selected by applying respective sets of values to the stores, the values representing characteristics of the stored pattern. A second binary value is assigned to all locations not selected. The pattern to be measured has sets of values representing characteristics thereof applied to respective addresses of the addressable data stores. The contents of the selected addresses are read and the binary values from the selected addresses are applied to a network capable of providing an output signal representing a selected binary value only when the first binary value is read from all selected locations. The output signal represents the result of the measurement and may provide a measure of the closeness of the stored and observed patterns.

Claims

1. A recognition procedure including the steps of teaching a reference pattern to a machine-based recognition system by writing a first binary digit to each of a plurality of addressable data stores, each of which has a plurality of addressable data storage locations, at locations selected by applying respective sets of values as addresses to the addressable data stores, where the sets of values represent characteristics of parts of the reference pattern, writing a second binary digit to all locations not selected in the addressable data stores, and of measuring another pattern against the reference pattern by applying, as addresses, to the addressable data stores, sets of values representing characteristics of parts of the other pattern, where the parts correspond to the said parts of the reference pattern, reading the contents of those locations selected, applying the binary digits read from the selected locations to a network that provides an output signal representing one binary digit as its output only when the first binary digit is obtained from each selected location, and which provides an output signal representing the other binary digit if one second binary digit is obtained from the selected locations, forming at least one sum of the total number of occurrences of the first binary digit at selected positions within the network, and providing a result signal indicating the result of the measurement, where the result signal is determined by the output signal from the network and the sum of the total number of occurrences of the first binary digit at selected positions within the network.

2. A recognition procedure as claimed in claim 1, wherein the first binary digit is a logical 1, and the network for providing the output signal is a network of logical AND gates.

3. A recognition procedure as claimed in claim 1, wherein the first binary digit is a logical 1, and the network includes a logic element capable of performing an AND operation on values presented to it, associated latches for storing respective input and output values for the logic element, and counters for controlling the grouping, and circulation, of successive input and output values, through the logic element, in group sizes, and for a number of times, as set by initial settings of the counters.

4. A recognition procedure as claimed in claim 1, which includes the steps of forming a sum of the total number of times that the first binary value is read from the addressable data stores during the measuring of the other pattern against the reference pattern, and taking the total number into account in providing an output signal indicating the result of the measurement.

5. A recognition procedure as claimed in claim 4, including the steps of forming sums of the total number of occurrences of the first binary value at selected positions within the network and taking those further sums into account in providing an output signal indicating the result of the measurement

6. A recognition procedure as claimed in claim 1, wherein the values representing characteristics of the reference pattern are encoded for application to the addressable data stores, and the encoding algorithm is different for each reference pattern.

7. A recognition procedure as claimed in claim 1, wherein the reference pattern relates to a human face.

8. A recognition procedure as claimed in claim 1, wherein the reference pattern is written to addressable data stores located in a machine-readable data carrier.

9. A recognition procedure as claimed in claim 1, which comprises making a pattern from a biometric determination of a person to be identified, reading a machine-readable data carrier having a reference pattern made from the same biometric determination of a person, comparing the two patterns, and indicating the identity or otherwise of the two patterns.

18. A machine-readable data carrier, produced by an apparatus as claimed in claim -7, including a plurality of addressable data stores, holding a reference pattern relating to human biometric characteristics.

10. An apparatus for carrying out a recognition procedure in which a reference pattern is memorized and a pattern to be examined is compared with the reference pattern, including:

a plurality of addressable data stores each having a plurality of addressable data storage locations, address ports, data input and output ports, and a read/write control port,

input means for receiving input values representing characteristics of a pattern to be memorized or examined and for presenting the input values as a plurality of sets of values to the address ports of respective ones of the addressable data stores,

a network of logic elements connected to the data output ports of the addressable data stores, the network being such as to provide one binary digit as its output only when a first binary digit is obtained from each data output port of the addressable data stores, and to provide the other binary digit if one second binary digit is obtained from the data output ports, and,

summation means connected to selected groups of logic elements in the network of logic elements for forming at least one total of the number of times the first binary digit appears at selected positions of the logic network,

the apparatus being operable, when a pattern is being memorized,

to load one location of each addressable data store with a first binary digit and to load all other locations with a second binary digit, where the locations that receive the first binary digit are selected by respective sets of the input values representing the characteristics of parts of the pattern being memorized, and

when a pattern is being examined,

to read the contents of one location of each addressable data store, where the locations that are read are selected by respective sets of the input values representing the characteristics of parts of the pattern being examined, where the parts correspond to the said parts of the memorized pattern,

to apply the data read from the addressable data stores to the network of logic elements, and,

to provide a result signal determined by the output signal from the network of logic elements and the output of the summation means.

11. An apparatus as claimed in claim 10, wherein the logic network consists of a cascade of groups of AND gates, in which the number of AND gates in each group is half the number of AND gates in the immediately preceding group.

12. An apparatus as claimed in claim 10, including a summation means for forming a sum of the total number of times that the first binary value is read from the addressable data stores during the examination of a pattern.

13. An apparatus as claimed in claim 12, including first summation means connected to the data output ports of the addressable data stores.

14. An apparatus as claimed in claim 13, including further summation means connected to selected groups of logic elements in the network of logic elements for forming further totals of the number of times the first binary value appears at selected parts of the logic network.

15. An apparatus as claimed in claims 10, wherein the input means is capable of encoding the input values for application to the addresses of the addressable data stores, and is capable of changing its encoding algorithm.

16. An apparatus as claimed in claims 10, which is capable of accepting a machine-readable data carrier in which is memorised a reference pattern relating to human biometric characteristics, of generating, as input values, values representing biometric characteristics of a subject presented for examination, and of performing the recognition procedure on the reference and generated biometric characteristics.

17. An apparatus as claimed in claims 10, including means for making a biometric determination, means for encoding the biometric determination, and means for applying the encoded data to a machine-readable data carrier.