Error preventive circuit for a photoelectric switch

• US 5,057,683 A
• Filed: 10/13/1989
• Issued: 10/15/1991
• Est. Priority Date: 10/28/1988
• Status: Expired due to Fees

• Current Assignee: Astex Company Limited, Takenaka Electronic IND Company Limited
• Original Assignee: Astex Company Limited, Takenaka Electronic IND Company Limited
• Inventors: Fukuyama, Toshifumi
• Primary Examiner(s): Nelms, David C.
• Application Number:
  US07/421,611
• Time in Patent Office: 732 Days
• Field of Search: 250/214 B, 250/214 R, 250/221, 250/222.1, 307/311
• US Class Current: 250/214.00B
• CPC Class Codes: H03K 17/16 Modifications for eliminating interference voltages or currents
• CPC Class Codes: H03K 17/78 using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled

Abstract

An error preventive circuit for a photoelectric switch is formed of a logic circuit, and it is highly responsive, while preventing erroneous operations caused by noises, eliminates the need of capacitors, and is suitable for circuit integration. The circuit validates the incoming light reception pulse only when its base-of-N counter has advanced to N counts, and, if the light reception pulse deviates in time by a certain value in the range of synchronism, a base-of-M counter is preset so that the timing of light reception is re-established at the center of the allowable range of synchronism.

Claims

1. An error preventive circuit for a photoelectric switch which operates in either transmission mode or reflection mode, whichever is selected, to detect an object by processing a light reception pulse by means of a plurality of comparators, wherein said circuit comprises:

a base-of-N counter which is clocked by a synchronous signal for the light reception pulse detection, a flip-flop which receives an in-phase light reception pulse as a set input and a drive signal for a light projector as a reset input, a means of latching the Q output of said flip-flop in response to a periodic signal provided by said counter and producing a detection output signal, an exclusive-OR gate which receives the Q output of said flip-flop and an inverted output of said latch means, and an AND gate (AND2) arranged to produce, in response to the output of said exclusive-OR gate and an inverted version of the synchronous signal, a high-level output, by which said counter is cleared.

2. An error preventive circuit for a photoelectric switch according to claim 1 further comprising a short circuit protection circuit which includes a first AND gate (AND5) arranged to produce a high-level output, in response to a specific value of said counter and a short-circuit signal which is created by the occurrence of a short-circuit on an output transistor or the like connected to the detection output signal of said switch;

a means of inverting the output of said AND gate (AND5); and

an second AND gate (AND4) arranged to block the detection output signal, in response to the output of the inverting means, said short-circuit protection circuit operating to invalidate the detection output signal if the short-signal lasts until said counter reaches said specific value.

3. An error preventive circuit for a photoelectric switch according to claim 1, wherein said latch means comprises a D-type flip-flop.

4. An error preventive circuit for a photoelectric switch according to claim 1, wherein said counter comprises an octal counter.

5. An error preventive circuit for a photoelectric switch according to claim 1, wherein the timing of said synchronous signal for entering a detection input is dependent on the selected mode of transmission or reflection.

6. An error preventive circuit for a photoelectric switch which operates in either transmission mode or reflection mode, whichever is selected, to detect an object by processing a light reception pulse by means of a plurality of comparators, said circuit comprising:

an oscillation circuit for generating a clock signal;

a base-of-M counter having a synchronous signal output with a certain duration for detecting a light reception pulse, outputs for a heading timing signal and a ending timing signal used in transmission mode and a preset input for presetting said counter to have a count value between the values of said heading and ending timing signals when the entry of the light reception pulse is coincident with the value of said heading timing signal or said ending timing signal; and

an AND gate (AND6) arranged to produce a highlevel output which is connected to the preset input of said counter, in response to a light reception pulse and heading and ending timing signals.

7. An error preventive circuit for a photoelectric switch according to claim 6, wherein the timing of said synchronous signal for entering a detection input is dependent on the selected mode of transmission or reflection.

8. An error preventive circuit for a photoelectric switch according to claim 6, additionally comprising a second AND gate (AND 7), arranged to produce a high-level output which is connected to the preset input of said counter, in response to an inverted transmission mode synchronous signal and a signal indicating said light reception pulse is outside the range of the value of said heading timing signal to the value of said ending timing signal.

9. An error preventive circuit for a photoelectric switch according to claim 6, wherein said oscillation circuit comprises a ring oscillator which includes an odd number of inverters in serial connection.

10. An error preventive circuit for a photoelectric switch according to claim 6, wherein said counter comprises a hexadecimal counter.