Switch interface for determining position of a plurality of switches using a determined time

• US 5,057,699 A
• Filed: 12/20/1989
• Issued: 10/15/1991
• Est. Priority Date: 12/20/1989
• Status: Expired due to Fees

• Current Assignee: Summit Business Capital Corp. (Bank of America Corp.)
• Original Assignee: Alliedsignal Inc.
• Inventors: Spence, James W.
• Primary Examiner(s): Pellinen, A. D.
• Assistant Examiner(s): ELMS, RICHARD T
• Application Number:
  US07/453,528
• Time in Patent Office: 664 Days
• Field of Search: 307/98, 307/99, 307/242, 307/241, 307/246, 341/147, 341/151, 333/172, 333/173, 364/483, 364/568
• US Class Current: 307/98
• CPC Class Codes: G05B 19/0423 Input/output
• CPC Class Codes: G05B 2219/21006 Detect position switches, connect resistances, analog value gives position
• CPC Class Codes: H03M 11/24 using analogue means , e.g. by coding the states of multiple switches into a single multi-level analogue signal or by indicating the type of a device using the voltage level at a specific tap of a resistive divider

Abstract

A circuit for interfacing switches to a component which allows the positions of the switches to be determined by the component. The component includes an input port and an output port. A switch network which is a parallel combination of two or more series combinations of a resistor and a switch is connected between the input and output port. A capacitor is connected between the input port and ground. The component determines switch positions by outputting a voltage on the output port and determining the time for the capacitor to charge to a predetermined value. Since each series combination has a unique resistance, the position of the switches therein can be determined in accordance with the capacitor charging time.

Claims

1. A switch interface, comprising:

a first port for selectively outputting a lower and a higher voltage;

a second port;

a plurality of series combinations of a switch and a resistor which are connected in a parallel circuit, each of said plurality of series combinations having a unique resistance and each of said switches being in an open or closed position, said parallel circuit having a first node connected to said first port and a second node connected to said second port;

a capacitor connected between said second port and a node biased at a reference voltage;

means for determining a time for a voltage at said second port to increase to a predetermined voltage level when said first port changes state from said lower voltage to said higher voltage; and

means for determining said position of each of said switches in accordance with said time.

2. The switch interface as claimed in claim 1, further comprising:

a plurality of ports for selectively outputting a lower and a higher voltage;

for each of said plurality of ports for selectively outputting a lower and a higher voltage, a plurality of series combinations of a switch and a resistor which are connected in parallel, each of said plurality of series combinations having a unique resistance and each of said switches being in an open or closed position, said parallel circuit having a first node connected to said port for selectively outputting one of two voltages and a second node connected to said second port.

3. The switch interface as claimed in claim 1, wherein said reference voltage node is grounded.

4. The switch interface as claimed in claim 1, wherein a Nth series combination in said plurality of series combinations has a resistance equal to R/2.sup.(N-1).

5. The switch interface as claimed in claim 1, wherein said plurality of switches are interfaced to a digital component wherein said first port initially outputs a LOW voltage and said second port is initially biased at said reference voltage, said component outputting a HIGH voltage at said first port when said position of each of said plurality of switches is to be determined.

6. The switch interface as claimed in claim 5, wherein said digital component is a microcontroller.

7. The switch interface as claimed in claim 5, wherein said digital component includes an internal timer to determine said time.

8. The switch interface as claimed in claim 5, wherein said predetermined voltage level is the switching threshold of said digital component.

9. The switch interface as claimed in claim 8, wherein said switching threshold is specified to be within a voltage range and said resistance of each of said plurality of series combinations is selected such that said voltage at said second port reaches said predetermined voltage at a unique range of times for each possible combination of switch positions.

10. The switch interface as claimed in claim 5, wherein the potential of said first port is changed from said lower voltage to said higher voltage said means for determining a time determines the time, t₁, for said voltage at said second port to switch from a LOW to a HIGH voltage and then the potential of said first port is changed from said higher voltage to said lower voltage and said means for determining a time determines the time for said voltage at said second port to switch from a HIGH to a LOW voltage.

11. A method of interfacing a plurality of switches to a component such that the component can determine the positions of each individual switch, the component having an input and an output port initially biased at a LOW voltage, the switch interface having a parallel combination of a plurality of series combinations of a switch and a resistor, the parallel combination being connected between the input and output port, each series combination having a unique resistance, and a capacitor connected between the input port and a node biased at a reference voltage, comprising the steps of:

outputting a HIGH voltage on the output port;

determining the time for the capacitor to charge to a predetermined voltage; and

determining the positions of the switches in accordance with the time.

12. The method as claimed in claim 11, wherein said predetermined voltage is the switching threshold of a digital component.

13. A method of interfacing a plurality of switches to a component such that the component can determine the position of each individual switch, the component having an input and an output port initially biased at a LOW voltage. The switch interface having a parallel combination, of a plurality of series combinations of a switch and a resistor, the parallel combination being connected between the input and output port, each series combination having a unique resistance, and a capacitor connected between the input port and a node biased at a reference voltage, comprising the steps of:

outputting a HIGH voltage on the output port;

determining the time for the capacitor to charge to a predetermined level;

outputting a LOW voltage on the output port;

determining the time for the capacitor to discharge to a predetermined level; and

determining the positions of the switches in accordance with the charging and discharging times.

14. The method as claimed in claim 13, wherein the capacitor is allowed to fully charge between outputting the HIGH and LOW voltages.

15. The method as claimed in claim 13, wherein said predetermined level is the switching point of a digital component.