Instruction storage method with a compressed format using a mask word

• US 5,057,837 A
• Filed: 01/30/1990
• Issued: 10/15/1991
• Est. Priority Date: 04/20/1987
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Colwell, Robert P., O'Donnell, John, Papworth, David B., Rodman, Paul K.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Kriess, Kevin A.
• Application Number:
  US07/476,108
• Time in Patent Office: 623 Days
• Field of Search: 382/56, 364/200, 364/900, 364/7.1, 358/23 C, 341/55, 341/59, 341/60, 341/63, 341/95, 341/56, 341/78, 341/106
• US Class Current: 341/55
• CPC Class Codes: G06F 12/0844 Multiple simultaneous or quasi-simultaneous cache accessing
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30149 of variable length instructions
• CPC Class Codes: G06F 9/30178 of compressed or encrypted instructions
• CPC Class Codes: G06F 9/321 Program or instruction counter, e.g. incrementing
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/3814 Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3828 with global bypass, e.g. between pipelines, between clusters
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters

Abstract

A method and apparatus for storing an instruction word in a compacted form on a storage media, the instruction word having a plurality of instruction fields, features associating with each instruction word, a mask word having a length in bits at least equal to the number of instruction fields in the instruction word. Each instruction field is associated with a bit of the mask word and accordingly, using the mask word, only non-zero instruction fields need to be stored in memory. The instruction compaction method is advantageously used in a high speed cache miss engine for refilling portions of instruction cache after a cache miss occurs.

Claims

1. A method for storing instruction words in a compressed format in a storage element of a data processor, each of the instruction words having N instruction fields, the method comprising the steps, performed by the data processor, of:

designating a plurality of mask words, one mask word corresponding to each of the instruction words, wherein each mask word has a length at least equal to N bits;

assigning each of the N instruction fields in each of the instruction words to one of the N bits of the corresponding mask word;

setting each of the N bits of each corresponding mask word to a first designation when its assigned instruction field is a non-zero instruction field;

setting each of the N bits of each corresponding mask word to a second designation when its assigned instruction field is a zero instruction field; and

storing each mask word and each corresponding non-zero instruction field in the storage element as a representation of the instruction words.

2. The method of claim 1 wherein the designating step further includes:

designating a plurality of mask words wherein each mask word has a length equal to N bits; and

wherein the first setting step further includes;

setting a number of N bits of each corresponding mask word to a non-zero value, the number of the N bits being equal to the number of first designations.

3. The method of claim 1 wherein the designating step further includes:

designating a plurality of instruction words to correspond each mask word; and

setting the number of bits of the mask word equal to the number of instruction fields in the corresponding instruction words.

4. The method of claim 1 further comprising the steps of:

grouping ones of the plurality of instruction words together as a word grouping;

wherein the plurality of mask words corresponding to the ones of the plurality of instruction words also correspond to the word grouping; and

formatting the representation of the instruction words in the storage element such that;

the representation of the word grouping begins with a mask word on a modulo-4 word boundary; and

the representation of the word grouping includes each other of the plurality of mask words in a set order, each other of the plurality of mask words beginning on a modulo-2 word boundary.

5. The method of claim 4, wherein:

each instruction field is thirty-two bits long;

each instruction word has at least thirty-two instruction fields; and

the formatting step includes spacing the plurality of mask words assigned to each word grouping from one another in the storage element by one non-zero instruction field.

6. A method for storing a plurality of very long instruction words in a compressed format in a data processor, wherein each of the instruction words has a plurality of instruction fields, the method comprising steps, performed by the data processor, of:

assigning a corresponding mask word to each of the plurality of instruction words, wherein each bit of the corresponding mask word is assigned to an instruction field of the instruction word;

setting each assigned bit of the corresponding mask word to a first designation when the assigned instruction field is a non-zero field;

setting each assigned bit of the corresponding mask word to a second designation when the assigned instruction field is a zero field; and

storing each corresponding mask word and each non-zero field in the storage element of the data processor.

7. The method of claim 6, wherein the storing step further includes:

storing the instruction words in the storage element as groups of instruction words; and

separating each corresponding mask word of the instruction words in a group of instruction words by at least one non-zero instruction field.

8. The method of claim 7, wherein the separating step further comprises separating each corresponding mask word of the instruction words in a group of instruction words by one non-zero instruction field.

9. The method of claim 7, wherein the storing step further includes:

storing non-zero instruction data of the instruction words to follow the corresponding mask word; and

separating the groups of instruction words by padding zeros. a second des