Video signal clamping circuit operating in the digital domain for removing excess noise on the black level and for providing d c restoration
First Claim
1. A video signal clamping circuit comprising:
- analog-to-digital converter means for converting an analog input video signal to a plurality of digital samples taken at a sampling frequency;
storage means for storing at least some of said plurality of digital samples during a portion of a horizontal blanking interval of the input video signal during which the signal is at a black level;
an error signal generator operative to generate a digital error signal representing any deviation between one of said plurality of digital samples supplied thereto from said storage means and a reference black level;
an accumulator operative to accumulate digital error signals supplied thereto by said error signal generator to produce an accumulated digital error signal;
a digital-to-analog converter for converting said accumulated digital error signal to an analog error signal;
clock means for controlling the supply of said stored plurality of digital samples in sequence from said storage means to said error signal generator such that said stored plurality of digital samples are supplied, during a line-active period that follows said horizontal blanking interval, at a clock frequency which is less than said sampling frequency; and
combining means for combining said analog error signal with said input video signal such that the black level of said input video signal approaches said reference black level.
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Accused Products
Abstract
In a video signal clamping circuit, a FIFO register stores a sequence of digital samples of an input video signal taken during a portion of a horizontal blanking interval of the signal during which the signal is at a black level. A black level error PROM generates a digital error signal representing any deviation between a digital sample from the FIFO register and a reference black level. An accumulator accumulates digital error signals supplied thereto by the PROM to produce an accumulated digital error signal which is converted to analog form by a digital-to-analog converter. A clock controls the supply of the stores samples in sequence from the FIFO register to the PROM such that the samples are supplied, during a line-active period that follows the horizontal blanking interval, at a clock frequency which is less than the sampling frequency. The analog error signal is combined with the input video signal in an operational amplifier to cause the black level of the input video signal to approach the reference black level.
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Citations
7 Claims
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1. A video signal clamping circuit comprising:
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analog-to-digital converter means for converting an analog input video signal to a plurality of digital samples taken at a sampling frequency; storage means for storing at least some of said plurality of digital samples during a portion of a horizontal blanking interval of the input video signal during which the signal is at a black level; an error signal generator operative to generate a digital error signal representing any deviation between one of said plurality of digital samples supplied thereto from said storage means and a reference black level; an accumulator operative to accumulate digital error signals supplied thereto by said error signal generator to produce an accumulated digital error signal; a digital-to-analog converter for converting said accumulated digital error signal to an analog error signal; clock means for controlling the supply of said stored plurality of digital samples in sequence from said storage means to said error signal generator such that said stored plurality of digital samples are supplied, during a line-active period that follows said horizontal blanking interval, at a clock frequency which is less than said sampling frequency; and combining means for combining said analog error signal with said input video signal such that the black level of said input video signal approaches said reference black level. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification