Semiconductor dies and wafers and methods for making

• US 5,059,899 A
• Filed: 08/16/1990
• Issued: 10/22/1991
• Est. Priority Date: 08/16/1990
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Farnworth, Warren D., Duesman, Kevin, Heitzeberg, Ed
• Primary Examiner(s): Weider, Kenneth A.
• Assistant Examiner(s): Nguyen, Vinh P.
• Application Number:
  US07/568,407
• Time in Patent Office: 432 Days
• Field of Search: 324/158 R, 324/158 T, 324/73.1, 324/537, 324/538, 357/40, 357/45, 307/303.1, 307/303, 371/15.1, 371/25.1, 437/8
• US Class Current: 438/18
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Disclosed is a method for producing individual semiconductor chips which are singulated from larger wafers, and singulated wafers produced according to the method. Wafers from which the singulated dies are produced include scribe line area through which the wafer is cut by a saw or other method for singulating individual dies. In one aspect of the invention, test pads are provided within the scribe line area for testing of individual dies prior to severing of the wafer. In another aspect of the invention, conventional test circuitry is formed within the scribe line area and utilized in conjunction with text pads for testing operability of individual wafers prior to severing of the wafer into individual chips. Upon test, the scribe lines are severed effectively destroying the sacrificial test pads and circuitry.

Claims

1. A semiconductor wafer comprising:

a plurality of individual dies containing integrated circuits, the dies containing at least one signal node;

scribe line area separating the dies to be severed through to cut the wafer into individual chips;

a conductive interface test pad formed in the scribe line area; and

a conductive interconnecting line extending from the at least one signal node to the conductive interface test pad in the scribe line area.

2. The semiconductor wafer of claim 1 wherein the conductive interconnecting line comprises induced voltage isolating circuitry formed within the individual dies.

3. The semiconductor wafer of claim 2 wherein the induced voltage isolating circuitry comprises a transistor within the die having a control line which is biased within the die to place the transistor in an off condition.

4. The semiconductor wafer of claim 1 wherein interconnecting lines extending from selected signal nodes from a plurality of dies are electrically connected in parallel with at least one selected interface test pads in the scribe line area to provide for simultaneous parallel testing of multiple dies.

5. The semiconductor wafer of claim 4 wherein the interconnecting lines extending from the selected signal nodes comprise induced voltage isolating circuitry formed within the individual dies.

6. The semiconductor wafer of claim 5 wherein the induced voltage isolating circuitry comprises a transistor within the individual dies, the transistor having a control line which is biased within the individual die to place the transistor in an off condition.

7. The semiconductor wafer of claim 1 further comprising integrated test circuitry formed within the scribe line area to facilitate testing of individual dies or groups of individual dies.

8. The semiconductor wafer of claim 7 wherein the conductive interconnecting line comprises induced voltage isolating circuitry formed within the individual dies.

9. The semiconductor wafer of claim 7 wherein the conductive interconnecting line comprises induced voltage isolating circuitry formed within the individual dies, and wherein the induced voltage isolating circuitry comprises a transistor within the die having a control line which is biased within the die to place the transistor in an off condition.

10. The semiconductor wafer of claim 7 wherein,

the conductive interconnecting line comprises induced voltage isolating circuitry formed within the individual dies;

the induced voltage isolating circuitry comprises a transistor within the die having a control line which is biased within the die to place the transistor in an off condition; and

the control line extends to and connects with the integrated test circuitry.

11. The semiconductor wafer of claim 7 wherein,

conductive interconnecting lines extending from selected signal nodes from a plurality of dies are electrically connected in parallel with at least one selected interface test pad in the scribe line area to provide for simultaneous parallel testing of multiple dies;

and

the conductive interconnecting lines comprise induced voltage isolating circuitry formed within the individual dies.

12. The semiconductor wafer of claim 7 wherein,

conductive interconnecting lines extending from selected signal nodes from a plurality of dies are electrically connected in parallel with at least one selected interface test pad in the scribe line area to provide for simultaneous parallel testing of multiple dies;

and

the conductive interconnecting lines comprise induced voltage isolating circuitry formed within the individual dies, the induced voltage isolating circuitry comprises a transistor within the die having a control line which is biased within the die to place the transistor in an off condition.

13. The semiconductor wafer of claim 12 wherein the control line extends to and connects with the integrated test circuitry.

14. A semiconductor wafer comprising:

a plurality of individual dies containing integrated circuits, the dies containing at least one signal node;

scribe line area separating the dies to be severed through to cut the wafer into individual chips;

integrated test circuitry formed within the scribe line area; and

a conductive interconnecting line extending from the at least one signal node to the integrated test circuitry formed within the scribe line area.

15. The semiconductor wafer of claim 14 wherein the conductive interconnecting line comprises induced voltage isolating circuitry formed within the individual dies.

16. The semiconductor wafer of claim 15 wherein the induced voltage isolating circuitry comprises a transistor within the die having a control line which is biased within the die to place the transistor in an off condition, the control line extending to and connecting with the integrated test circuitry.

17. A method of fabricating a semiconductor wafer comprising the following steps:

processing a semiconductor wafer to form a plurality of individual dies containing integrated circuits and at least one signal node, the individual dies being formed on the wafer to define severing scribe line area between individual dies;

forming at least one conductive interface test pad in the scribe line area;

forming conductive interconnecting lines which extend from a plurality of signal nodes from different individual dies to the at least one conductive interface test pad in the scribe line area;

testing individual dies in parallel by contacting a test probe with the at least one conductive interface test pad;

designating which of the tested individual dies are defective;

severing through the scribe line area, the conductive interface test pad, and interconnecting lines within the scribe line area, to form individual chips; and

collecting operable chips.

18. The method of fabricating a semiconductor wafer of claim 17 further comprising forming induced voltage isolating circuitry within individual dies to selectively isolate the at least one signal node from selected portions of the conductive interconnecting lines extending therefrom.

19. The method of fabricating a semiconductor wafer of claim 17 further comprising forming integrated test circuitry within the scribe line area, the conductive interconnecting lines extending from individual dies to the integrated test circuitry and from there selectively to conductive interface test pads in the scribe line area.

20. The method of fabricating a semiconductor wafer of claim 17 further comprising:

forming induced voltage isolating circuitry within individual dies to selectively isolate the at least one signal node from selected portions of the conductive interconnecting lines extending therefrom; and

forming integrated test circuitry within the scribe line area, the conductive interconnecting lines extending from individual dies to the integrated test circuitry and from there selectively to conductive interface test pads in the scribe line area.

21. A method of fabricating a semiconductor wafer comprising the following steps:

processing a semiconductor wafer to form a plurality of individual dies containing integrated circuits and at least one signal node, the individual dies being formed on the wafer to define severing scribe line area between individual dies;

forming integrated test circuitry within the scribe line area;

forming conductive interconnecting lines which extend from a plurality of signal nodes from different individual dies to the integrated test circuitry within the scribe line area;

testing individual dies by using the integrated test circuitry within the scribe line area;

designating which of the tested individual dies are defective;

severing through the scribe line area, the interconnecting lines within the scribe line area, and the integrated test circuitry within the scribe line area, to form individual chips; and

collecting operable chips.

22. The method of fabricating a semiconductor wafer of claim 21 further comprising forming induced voltage isolating circuitry within individual dies to selectively isolate the at least one signal node from selected portions of the conductive interconnecting lines extending therefrom.