Method and apparatus for transparently switching clock sources

• US 5,059,925 A
• Filed: 09/28/1990
• Issued: 10/22/1991
• Est. Priority Date: 09/28/1990
• Status: Expired due to Term

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: StrataCom, Inc. (Cisco Systems, Inc.)
• Inventors: Weisbloom, John D.
• Primary Examiner(s): Pascal, Robert J.
• Application Number:
  US07/590,668
• Time in Patent Office: 389 Days
• Field of Search: 331/1 A, 331/16, 331/18, 331/25, 328/133, 328/134, 328/155
• US Class Current: 331/1.00A
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H04J 3/0688 Change of the master or reference, e.g. take-over or failure of the master
• CPC Class Codes: H04L 7/0083 taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Abstract

A method and apparatus for stably maintaining an output clock signal from a phase-locked loop (PLL) frequency multiplier when switching from one clock source to another clock source is described. This method and apparatus maintains the phase relationship between the external signal to the phase detector and the feedback signal from the divider to the phase detector.

Claims

1. A circuit for maintaining a stable output from a phase-locked loop frequency multiplier circuit, comprising a phase detector, a voltage controlled oscillator, and a divider, when switching an input to said phase-locked loop frequency multiplier circuit from a first input signal to a second input signal, comprising:

(a) a load circuit coupled to receive as a first input an output of said divider of said phase-locked loop frequency multiplier circuit, said load circuit changing its output load signal from a first type of state to a second type of state when said second input signal is selected and the output of said divider changes from said first type of state to said second type of state, said divider of said phase-locked loop frequency multiplier circuit coupled to receive said load signal, said divider cleared when said load signal is in said second type of state;

(b) a first switch coupled to receive said first input signal and said second input signal, said first switch for switching its output from said first input signal to said second input signal when said second input signal is selected, said load circuit coupled to receive as a second input said first switch output signal, said load circuit changing said load signal from said second type of state to said first type of state when said second input signal is selected and said first switch output signal changes from said first type of state to said second type of state, said load signal in said first type of state causing said divider of said phase-locked loop frequency multiplier circuit to continue counting;

(c) a second switch coupled to receive said first input signal, said second input signal, and said load signal, said second switch for switching its output from said first input signal to said second input signal when said second input signal is selected and said load signal changes from said second type of state to said first type of state;

(d) a logic circuit coupled to receive said load signal and said second switch output signal, said logic circuit for generating the logical AND of said load signal and said second switch output signal, said logic circuit output coupled to the input of said phase-locked loop frequency multiplier circuit.

2. The circuit for maintaining a stable output from a phase-locked loop frequency multiplier of claim 1, wherein said first type of state is a high state and said second type of state is a low state.

3. A circuit for maintaining a stable output from a phase-locked loop frequency multiplier circuit, comprising an exclusive-OR circuit, a voltage controlled oscillator, and a divider, when switching an input to said phase-locked loop frequency multiplier circuit from a first input signal to a second input signal, comprising:

(a) a load circuit coupled to receive as a first input an output of said divider of said phase-locked loop frequency multiplier circuit, said load circuit changing its output load signal from a first type of state to a second type of state when said second input signal is selected and the output of said divider changes from said first type of state to said second type of state, said divider of said phase-locked loop frequency multiplier circuit coupled to receive said load signal, said divider cleared when said load signal is in said second type of state;

(b) a first switch coupled to receive said first input signal and said second input signal, said first switch for switching its output from said first input signal to said second input signal when said second input signal is selected, said load circuit coupled to receive as a second input said first switch output signal, said load circuit changing said load signal from said second type of state to said first type of state when said second input signal is selected and said first switch output signal changes from said first type of state to said second type of state, said load signal in said first type of state causing said divider of said phase-locked loop frequency multiplier circuit to continue counting;

(c) a second switch coupled to receive said first input signal, said second input signal, and said load signal, said second switch for switching its output from said first input signal to said second input signal when said second input signal is selected and said load signal changes from said second type of state to said first type of state;

(d) a logic circuit coupled to receive said load signal and said second switch output signal, said logic circuit for generating the logical AND of said load signal and said second switch output signal, said logic circuit output coupled to the input of said phase-locked loop frequency multiplier circuit.

4. The circuit for maintaining a stable output from a phase-locked loop frequency multiplier of claim 3, wherein said first type of state is a high state and said second type of state is a low state.

5. A circuit for maintaining a stable output from a phase-locked loop frequency multiplier circuit, comprising a phase detector, a voltage controlled oscillator, and a divider, when switching an input to said phase-locked loop frequency multiplier circuit from a first input signal to a second input signal, comprising:

(a) a load circuit coupled to receive as a first input an output of said divider of said phase-locked loop frequency multiplier circuit, said load circuit changing its output load signal from a first type of state to a second type of state when said second input signal is selected and the output of said divider changes from said first type of state to said second type of state, said divider of said phase-locked loop frequency multiplier circuit coupled to receive said load signal, said divider cleared when said load signal is in said second type of state;

(b) a first switch coupled to receive said first input signal and said second input signal, said first switch for switching its output from said first input signal to said second input signal when said second input signal is selected, said load circuit coupled to receive as a second input said first switch output signal, said load circuit changing said load signal from said second type of state to said first type of state when said second input signal is selected and said first switch output signal changes from said first type of state to said second type of state, said load signal in said first type of state causing said divider of said phase-locked loop frequency multiplier circuit to continue counting;

(c) a second switch coupled to receive said first input signal, said second input signal, and said load signal, said second switch for switching its output from said first input signal to said second input signal when said second input signal is selected and said load signal changes from said second type of state to said first type of state;

(d) a logic circuit coupled to receive said load signal and said second switch output signal, said logic circuit for generating the logical OR of said load signal and said second switch output signal, said logic circuit output coupled to the input of said phase-locked loop frequency multiplier circuit.

6. The circuit for maintaining a stable output from a phase-locked loop frequency multiplier of claim 5, wherein said first type of state is a low state and said second type of state is a high state.

7. A method of maintaining a stable output from a phase-locked loop frequency multiplier circuit, comprising a phase detector, a voltage controlled oscillator, and a divider, when switching an input to said phase-locked loop frequency multiplier circuit from a first input signal to a second input signal, comprising the steps of:

(a) continuously clearing the divider of said phase-locked loop frequency multiplier circuit when said first input signal changes from a first type of state to a second type of state;

(b) holding the input to said phase-locked loop frequency multiplier circuit in said second type of state;

(c) no longer clearing the divider of said phase-locked loop frequency multiplier circuit when said second input signal changes from said second type of state to said first type of state;

(d) switching the input to said phase-locked loop frequency multiplier circuit from said first input signal to said second input signal when said second input signal is in said second type of state and before the divider of said phase-locked loop frequency multiplier circuit has continued counting and outputted a change in type of state.

8. The method of maintaining a stable output from a phase-locked loop frequency multiplier of claim 7 wherein said first type of state is a high state and said second type of state is a low state.

9. The method of maintaining a stable output from a phase-locked loop frequency multiplier of claim 7, wherein said first type of state is a low state and said second type of state is a high state.

10. A method of maintaining a stable output from a phase-locked loop frequency multiplier circuit, comprising an exclusive-OR circuit, a voltage controlled oscillator, and a divider, when switching an input to said phase-locked loop frequency multiplier circuit from a first input signal to a second input signal, comprising the steps of:

(a) continuously clearing the divider of said phase-locked loop frequency multiplier circuit when said first input signal changes from a first type of state to a second type of state;

(b) holding the input to said phase-locked loop frequency multiplier circuit in said second type of state;

(c) no longer clearing the divider of said phase-locked loop frequency multiplier circuit when said second input signal changes from said second type of state to said first type of state;

(d) switching the input to said phase-locked loop frequency multiplier circuit from said first input signal to said second input signal when said second input signal is in said second type of state and before the divider of said phase-locked loop frequency multiplier circuit has continued counting and outputted a change in type of state.