Screen blanker for a monitor of a computer system

• US 5,059,961 A
• Filed: 08/21/1989
• Issued: 10/22/1991
• Est. Priority Date: 08/21/1989
• Status: Expired due to Fees

• Current Assignee: Te J. Cheng
• Original Assignee: Te J. Cheng
• Inventors: Cheng, Te J.
• Primary Examiner(s): Weldon, Ulysses
• Application Number:
  US07/397,059
• Time in Patent Office: 792 Days
• Field of Search: 340/720, 340/811, 307/125, 307/126, 307/141, 307/141.4, 358/190, 358/220, 358/165, 371/16.3
• US Class Current: 345/10
• CPC Class Codes: G09G 1/16 the pattern of rectangular co-ordinates extending over the whole area of the screen, i.e. television type raster
• CPC Class Codes: G09G 2320/046 Dealing with screen burn-in prevention or compensation of the effects thereof
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving

Abstract

The present invention discloses a screen blanker for a monitor of a computer system, which will automatically clear the data image on the display screen of a monitor of a computer system after the computer has not been operated for a predetermined time period, and the data image which had disappeared will reappear once again on the display screen of the monitor after data is keyed in again by the operator. By this, the display screen of the monitor of the computer system can be protected from getting burned images thereon.

Claims

1. A screen blanker for a video monitor of a computer system having a CPU, a video RAM connected to said CPU, and a CRT controller connected to said CPU, said video monitor being connected to said CRT controller and said screen blanker, said video monitor having a first input terminal and a second input terminal for receiving a vertical synchronizing signal and horizontal synchronizing signal respectively, said screen blanker comprising:

a first input terminal, a second input terminal and a third input terminal, said first input terminal being connectable between said CPU and said video RAM for receiving a memory write/read signal from said video RAM, said second input terminal and third input terminal being connectable to said CRT controller, for respectively receiving the horizontal synchronizing signal and the vertical synchronizing signal from said CRT controller;

a first output terminal and a second output terminal for providing said vertical synchronizing signal and horizontal synchronizing signal, respectively, to said first and second input terminals of said video monitor;

a timer comprising a first counter, a second counter, a third counter and a fourth counter, said counters being interconnected to provide timing intervals, a first input terminal of said first counter being connected to an output terminal of a first inverter, and an input terminal of said first inverter forming said third input terminal of said screen blanker for receiving the vertical synchronizing signal from said CRT controller, a first input terminal of said second counter being connected to an output terminal of a second inverter, and an input terminal of said second inverter forming said first input terminal of said screen blanker for receiving the memory write/read signal from said video RAM, said fourth counter being provided with a first output terminal, a second output terminal and a third output terminal;

a time selector capable of being connected to a desired one of said first, second, or third output terminals of said fourth counter of said timer;

a detector connected between said time selector and said first input terminal of said second counter of said timer, said detector comprising a third inverter, a fourth inverter and an RS flip-flop, said RS flip-flop being comprised of a first NAND gate and a second NAND gate, an output terminal of the second NAND gate forming an output terminal of said detector; and

a video signal controller connected to said output terminal of said detector and said third input terminal of said screen blanker, said video signal controller comprising a third NAND gate, a fourth NAND gate, a fifth inverter and a sixth inverter, said fifth inverter and said sixth inverter being respectively connected in series with said third NAND gate and said fourth NAND gate, a first input terminal of said third NAND gate and a first input terminal of said fourth NAND gate being connected to said output terminal of said detector, a second input terminal of said third NAND gate being connected to said third input terminal of said screen blanker, a second input terminal of said fourth NAND gate being connected to said second input terminal of said screen blanker, the output terminals of said fifth inverter and said sixth inverter forming, respectively, said first and second output terminals of said screen blanker.