Back-sampling analog to digital converter

• US 5,059,982 A
• Filed: 09/24/1990
• Issued: 10/22/1991
• Est. Priority Date: 04/20/1989
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Bacrania, Kantilal, Chi, Chong I.
• Primary Examiner(s): Williams, Howard L.
• Application Number:
  US07/587,089
• Time in Patent Office: 393 Days
• Field of Search: 341/122, 341/153, 341/150, 341/155, 341/157, 341/161, 341/162, 341/172
• US Class Current: 341/172
• CPC Class Codes: H03M 1/0836 of phase error, e.g. jitter
• CPC Class Codes: H03M 1/466 using switched capacitors
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

Analog to digital conversion begins by terminating the acquisition phase of the analog input signal and immediately starting the successive approximation conversion phase upon receipt of a start conversion command. Upon the completion of the successive approximation conversion phase and latching the result, the array is rest if required. The comparator offset is sampled-and-held, if required, and the acquisition phase is initiated and continues until the receipt or occurrence of the next start conversion command.

Claims

1. A method of performing analog to digital conversion using an array, comprising in sequence:

terminating acquisition of an analog input signal upon occurrence of a start conversion command;

successively approximating a digital value of said analog input signal using said array;

fixing said digital value upon completion of said successive approximation; and

initiating acquisition of an analog input signal after fixing said digital value and before a leading edge of said start conversion command.

2. A method according to claim 1, wherein said approximating begins immediately after termination of acquisition.

3. A method according to claim 1, wherein acquisition includes initiating sampling of said analog signal from after completion of said approximating step and holding said sampled signal upon occurrence of said start conversion command.

4. A method according to claim 1, including resetting said array after said fixing step.

5. A method according to claim 4, wherein said resetting step and said initiating acquisition step occur simultaneously.

6. A method according to claim 1, wherein said successively approximating includes:

successively storing digital values in a register;

converting stored digital values into analog values using said array; and

comparing converted analog values with acquired analog input signal.

7. In an analog to digital converter having an analog input means, a digital to analog converter means, a successive approximation register means, comparator means for comparing an analog input signal acquired by said analog input means with an analog signal converted by said converter means from a digital signal from said register means, digital output means and control means responsive to a start conversion command for controlling the sequence of acquisition of an input analog signal by said analog input means, resetting said converter means, successive approximation of a digital value of an acquired analog input signal by said converter, comparator and register means and outputting a digital value on said digital output means, the improvement comprising said control means which in response to a start conversion command produces in sequence:

termination of acquisition of an input analog signal by said analog input means;

successively approximating a digital value of said acquired analog input signal by said converter, comparator and register means;

outputting said digital value on said digital output upon completion of said successive approximation; and

initiating acquisition of an input analog signal after fixing said digital value and before a leading edge of said start conversion command.

8. A converter according to claim 7, wherein said control means initiates said successive approximation immediately after termination of acquisition.

9. A converter according to claim 7, wherein said converter means includes a binary weighted array.

10. A converter according to claim 7, wherein said array is a resistive R-2R array.

11. A converter according to claim 7, wherein said analog input means includes a sample and hold and said control means controls said analog input means to initiate sampling of said analog signal from after completion of approximation and holding said sampled signal upon occurrence of said start conversion command.

12. A converter according to claim 7, wherein said control means resets said converter means and initiates acquisition simultaneously.