Complementary heterojunction field effect transistor with an anisotype N+ g a -channel devices

• US 5,060,031 A
• Filed: 09/18/1990
• Issued: 10/22/1991
• Est. Priority Date: 09/18/1990
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Abrokwah, Jonathan K., Huang, Jenn-Hwa, Wu, Schyi-Yi
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US07/584,014
• Time in Patent Office: 399 Days
• Field of Search: 357/22 A, 357/22 MD, 357/22, 357/16
• US Class Current: 257/274
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 29/802 with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors H01L29/806 takes precedence; with one dimensional electron gas H01L29/775; with dimensional electron gas H01L29/778

Abstract

A GaAs complementary HFET structure having an anisotype layer formed underneath the P-channel device gate is provided. The anisotype layer is heavily doped N-type and is formed in contact with a semi-insulating AlGaAs barrier of the P-channel FET. A pre-ohmic layer is formed over the anisotype layer and a gate electrode is formed over the pre-ohmic layer. In a first embodiment, the pre-ohmic layer comprises undoped gallium arsenide amd the gate electrode forms a Schottky diode with the pre-ohmic layer. The anisotype layer forms a semiconductor junction with the semi-insulating AlGaAs barrier wherein the semiconductor junction replaces or augments a conventional Schottky junction. In a second embodiment, the pre-ohmic layer comprises heavily doped InGaAs and the gate electrode forms an ohmic contact to the doped InGaAs. The semiconductor junction at the P-channel device gate results in higher built in potential barrier and improved P-channel gate turn on voltage.

Claims

1. A complementary GaAs based heterostructure integrated circuit structure comprising:

a semi-insulating GaAs substrate having a major surface;

a first epitaxial layer of substantially intrinsic GaAs grown directly over the major surface;

a second epitaxially grown layer of substantially intrinsic AlGaAs grown directly over the first layer;

a third epitaxially grown layer of substantially intrinsic GaAs grown over the second layer;

a fourth epitaxial layer of substantially intrinsic InGaAs grown over the third layer;

a fifth epitaxial layer of substantially intrinsic AlAs grown over the fourth layer;

a sixth layer of substantially intrinsic AlGaAs grown over the fifth layer;

first and second N-type regions formed in the surface of the sixth layer and extending to the third layer, wherein a portion of the fourth layer which lies between the first and second N-type regions forms a channel of an N-channel HFET;

a conductive material formed on top of the sixth layer between and separated from the first and second N-type regions and making a rectifying contact with the sixth layer, wherein the conductive material serves as a gate electrode of the N-channel HFET;

electrodes formed on the first and second N-type regions to serve as source-drain electrodes of the N-channel HFET;

first and second P-type regions formed in the surface of the sixth layer and extending to the third layer, wherein a portion of the fourth layer which lies between the first and second P-type regions forms a channel of a P-channel HFET;

an epitaxially grown N-type anisotype region covering a portion of the sixth layer between and separated from the first and second P-type regions;

an epitaxially grown pre-ohmic layer covering the N-type anisotype region;

a conductive material formed on top of the pre-ohmic layer making contact with the pre-ohmic layer, wherein the conductive material serves as a gate electrode of the P-channel HFET;

electrodes formed on the first and second P-type regions to serve as source-drain electrodes of the P-channel HFET; and

an insulating region formed between the N-channel and the P-channel HFET.

2. The integrated circuit of claim 1 wherein the pre-ohmic layer comprises an epitaxially grown layer of substantially intrinsic GaAs, and the contact between the gate electrode and the pre-ohmic layer is a rectifying contact.

3. The integrated circuit of claim 1 wherein the pre-ohmic layer comprises an epitaxially grown layer of N-type InGaAs which is graded in composition from GaAs at an interface with the anisotype region to a composition of In_x Ga_1-x As at an interface with the gate electrode, where x is greater than or equal to 0.5.

4. The integrated circuit of claim 1 wherein the epitaxially grown N-type anisotype region has a thickness in the range of 200 to 500 angstroms and a substantially uniform doping concentration of at least 5×

10¹⁸ atoms/cm³.

5. A complementary HFET structure having N-channel and P-channel HFET devices, the improvement comprising:

at least a single delta-doped N-type anisotype layer formed under a gate electrode of the P-channel HFET device;

a pre-ohmic layer formed between the N-type anisotype layer and the gate electrode, wherein the gate electrode makes an electrical contact to the pre-ohmic layer.

6. The HFET of claim 5 wherein the pre-ohmic layer comprises an epitaxially grown layer of substantially intrinsic GaAs and the electrical contact from the gate electrode to the pre-ohmic layer is rectifying.

7. The HFET of claim 5 wherein the pre-ohmic layer comprises an epitaxially grown layer of N-type InGaAs which is graded in composition from GaAs at an interface with the N-type anisotype layer to a composition of In_x Ga_1-x As at an interface with the gate electrode, where x is greater than or equal to 0.5 and the electrical contact to the pre-ohmic layer is substantially ohnmic.

8. The HFET of claim 5 wherein threshold voltage of the N-channel device is controlled by N-type dopant which is implanted into a channel and a semi-insulating region of the N-channel device.

9. The HFET of claim 5 wherein the N-channel and P-channel devices are separated by an isolation region comprising an oxygen implanted semiconductor region.

10. A complementary GaAs heterostructure field effect transistor structure comprising:

an N-channel field effect transistor having gate, drain, and source electrodes;

a P-channel field effect transistor having gate, drain, and source electrodes;

an intrinsic channel region located underneath the gate electrode;

a barrier region located between the channel region and the gate electrode;

an n-type delta-doped region formed on the barrier region; and

an intermediate layer of material coupling the gate electrode of the P-channel device to the n-type delta-doped region, wherein the material for coupling has a bandgap no greater than a bandgap of the delta-doped region.

11. The complementary field effect transistor structure of claim 10 wherein the barrier region comprises a layer of intrinsic AlGaAs between the channel region and the N-type delta-doped region.

12. A P-channel HFET having a gate electrode, a source electrode, a drain electrode, a channel region, and a semi-insulating region formed between the gate electrode and the channel region, the improvement comprising:

an N-type region formed underneath the gate electrode and in contact with the semi-insulating region so as to make a rectifying coupling between the gate electrode and the semi-insulating region; and

a means for preventing depletion of the N-type region formed between the N-type region and the gate electrode.