Futurebus interrupt subsystem apparatus

• US 5,060,139 A
• Filed: 04/07/1989
• Issued: 10/22/1991
• Est. Priority Date: 04/07/1989
• Status: Expired due to Term

• Current Assignee: American Video Graphics LP
• Original Assignee: Tektronix Incorporated (Fortive Corp.)
• Inventors: Theus, John G.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): PAN, DANIEL H
• Application Number:
  US07/335,027
• Time in Patent Office: 928 Days
• Field of Search: 340/825.50, 364/200 MS File, 364/900 Ms File
• US Class Current: 710/123
• CPC Class Codes: G06F 13/26 with priority control
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 13/4031 with arbitration

Abstract

An interface circuit board connected to a VMEbus standard backplane bus of a first data processing system, and also to a Futurebus standard backplane bus of a second data processing system, provides address/data conversion and interrupt service between the two standard bus structures. The Futurebus, being a higher level bus than the VMEbus, has no provision for hardware interrupts; event related data are conventionally transmitted across the Futurebus like any other data item. The interface board signals VMEbus interrupts to Futurebus devices by way of the Futurebus bus arbitration facility. Interrupts generated on the interface circuit board and interrupts from the VMEbus priority interrupt bus are mapped and converted into message numbers, one of which is asserted on the Futurebus arbitration bus as an arbitration number higher than the arbitration numbers assigned to Futurebus devices. Upon winning the arbitration for the Futurebus, the interface board, instead of acquiring it, releases the bus after the devices on the bus have registered the message, which thereby becomes an interrupt across the bus.

Claims

1. In a data processing system having a plurality of modular devices each connected asynchronously to a standard backplane bus and including a distributed-logic arbitration controller resolving contention for access to the standard backplane bus among the plurality of modular devices and communicating with each of the plurality of modular devices for the purpose of arbitration by way of an arbitration bus of the standard backplane bus, wherein each of the plurality of modular devices contending for access to the bus during an arbitration cycle asserts a unique arbitration number on the arbitration bus, the arbitration controller granting control of the standard backplane bus to one of the contending modular devices in accordance with a predetermined order of priority of the arbitration numbers of the plurality of modular devices, the arbitration controller, prior to granting such control to the one contending modular device, releasing from the arbitration bus the arbitration numbers of other contending modular devices, the arbitration number of the one contending modular device remaining asserted on the arbitration bus for recording by the plurality of modular devices, at least one of the modular devices having an event-driven interrupt signal source, the improvement comprising a method of transmitting an event-driven interrupt signal from one of the plurality of modular devices to all of the other modular devices across the standard backplane bus, the method comprising the steps of:

converting in the at-least-one of the modular devices the event-driven interrupt signal to an interrupt message number having a priority higher than the arbitration numbers of the plurality of modular devices;

initiating an arbitration cycle from the at-least-one of the modular devices;

asserting the interrupt message number on the arbitration bus during a bus arbitration cycle; and

relinquishing control of the standard backplane bus after such control is granted to the at-least-one of the modular devices by the arbitration controller, the interrupt message having been recorded by the plurality of modular devices.

2. In an interface circuit module transferring data between first and second data processing systems and connected between a first backplane bus of the first data processing system and a second backplane bus of the second data processing system, the first backplane bus including a priority interrupt bus and a data transfer bus communicating with the interface circuit module, the second backplane bus including an arbitration bus and an address/data bus communicating with the interface module, the second data processing system including a plurality of modular devices connected to the second backplane bus and contending for access to the second backplane bus by way of the arbitration bus during an arbitration cycle, each of the plurality of devices having a unique arbitration number of predetermined priority by which access to the backplane bus is asserted and granted during the bus arbitration cycle, each of the plurality of devices including means for registering the arbitration number of a device granted bus access during the arbitration cycle, apparatus for transmitting a priority interrupt signal from the priority interrupt bus to devices connected to the second backplane bus, the apparatus comprising:

means in the interface circuit module for receiving the interrupt signal;

means coupled to the receiving means for generating an interrupt message having a higher priority than the unique arbitration numbers; and

means for asserting the interrupt message on the arbitration bus as an arbitration number during an arbitration cycle, thereby transmitting the interrupt message to the plurality of devices across the second backplane bus.

3. The apparatus according to claim 2 further comprising means in the interface circuit module for releasing control of the second backplane bus during the arbitration cycle after the plurality of devices connected to the second backplane bus have registered the interrupt message.