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Semiconductor memory device having a BICMOS memory cell

  • US 5,060,194 A
  • Filed: 03/28/1990
  • Issued: 10/22/1991
  • Est. Priority Date: 03/31/1989
  • Status: Expired due to Term
First Claim
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1. A semiconductor memory device comprising:

  • a plurality of word lines;

    a plurality of bit lines;

    an array of memory cells each including a bipolar transistor which has a base, an emitter and a collector and a switching transistor connected between the base of said bipolar transistor and a corresponding one of said plurality of bit lines and controlled by a corresponding one of said plurality of word lines;

    means for controlling a collector-emitter voltage applied to said bipolar transistor so that the polarity of a base current changes due to impact ionization as a base-emitter voltage applied to said bipolar transistor is increased and so that a potential corresponding to a base-emitter voltage at a boundary between forward and reverse base currents is used as a writing potential; and

    voltage-variable means for varying an emitter voltage of a memory cell selected by one of said plurality of word lines to have the collector-emitter voltage higher in a memory cell data readout operation than in a case wherein the memory cell is not selected.

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