Semiconductor memory device having a BICMOS memory cell
First Claim
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1. A semiconductor memory device comprising:
- a plurality of word lines;
a plurality of bit lines;
an array of memory cells each including a bipolar transistor which has a base, an emitter and a collector and a switching transistor connected between the base of said bipolar transistor and a corresponding one of said plurality of bit lines and controlled by a corresponding one of said plurality of word lines;
means for controlling a collector-emitter voltage applied to said bipolar transistor so that the polarity of a base current changes due to impact ionization as a base-emitter voltage applied to said bipolar transistor is increased and so that a potential corresponding to a base-emitter voltage at a boundary between forward and reverse base currents is used as a writing potential; and
voltage-variable means for varying an emitter voltage of a memory cell selected by one of said plurality of word lines to have the collector-emitter voltage higher in a memory cell data readout operation than in a case wherein the memory cell is not selected.
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Abstract
A semiconductor memory device includes a plurality of memory cells each having a bipolar transistor whose collector-emitter voltage VCE is controlled according to the base potential to satisfy the condition of IBE <ICB when the forward base current in the base-emitter path and the reverse base current in the collector-base path are respectively expressed by IBE and ICB and a switching element connected to the bipolar transistor, word lines, bit lines and emitter electrode lines connected to the memory cells, and functions as a dynamic memory cell in the data storing operation and as a gain memory cell in the readout operation.
25 Citations
21 Claims
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1. A semiconductor memory device comprising:
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a plurality of word lines; a plurality of bit lines; an array of memory cells each including a bipolar transistor which has a base, an emitter and a collector and a switching transistor connected between the base of said bipolar transistor and a corresponding one of said plurality of bit lines and controlled by a corresponding one of said plurality of word lines; means for controlling a collector-emitter voltage applied to said bipolar transistor so that the polarity of a base current changes due to impact ionization as a base-emitter voltage applied to said bipolar transistor is increased and so that a potential corresponding to a base-emitter voltage at a boundary between forward and reverse base currents is used as a writing potential; and voltage-variable means for varying an emitter voltage of a memory cell selected by one of said plurality of word lines to have the collector-emitter voltage higher in a memory cell data readout operation than in a case wherein the memory cell is not selected. - View Dependent Claims (2, 3)
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4. A semiconductor memory device comprising:
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a plurality of word lines; a plurality of bit lines; an array of memory cells each including a bipolar transistor which has a base, an emitter and a collector and a switching transistor connected between the base of said bipolar transistor and a corresponding one of said plurality of bit lines and controlled by a corresponding one of said plurality of word lines; means for controlling a collector-emitter voltage applied to said bipolar transistor so that the polarity of a base current changes due to impact ionization as a base-emitter voltage applied to said bipolar transistor is increased and so that a potential corresponding to a base-emitter voltage at a boundary between forward and reverse base currents is used as a writing potential; voltage-variable means for varying an emitter voltage of a memory cell selected by one of said plurality of word lines to have the collector-emitter voltage higher in a memory cell data readout operation than in a case wherein the memory cell is not selected; and a plurality of emitter electrode lines arranged in parallel with said word lines, each emitter electrode line being selectable by an address. - View Dependent Claims (5, 6, 7, 8, 9)
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10. A semiconductor memory device comprising:
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a plurality of word lines; a plurality of bit lines; a memory cell array including a plurality of memory cells arranged in a matrix form, each memory cell including a bipolar transistor which has a base, an emitter, a collector, and a PN junction between the base and the emitter and a switching transistor connected between the base of said bipolar transistor and a corresponding one of said plurality of bit lines and controlled by a corresponding one said plurality of word lines; means for controlling a collector-emitter voltage applied to said bipolar transistor so that the polarity of a base current changes due to impact ionization as a base-emitter voltage applied to said bipolar transistor is increased and so that a potential corresponding to a base-emitter voltage at a boundary between forward and reverse base currents is used as a writing potential; voltage-variable means for varying an emitter voltage of each memory cell so as to set the PN junction between the base and emitter of said bipolar transistor into a forward bias state for a preset period of time at least once in a predetermined cycle irrespective of whether said plurality of word lines are selected or non-selected; and a plurality of emitter electrode lines, each emitter electrode line being selectable by an address. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A semiconductor memory device comprising:
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a plurality of word lines; a plurality of bit lines; a memory cell array including a plurality of memory cells arranged in a matrix form, each memory cell including a bipolar transistor which has a base, an emitter, a collector, and a PN junction between the base and the emitter and a switching transistor connected between the base of said bipolar transistor and a corresponding one of said plurality of bit lines and controlled by a corresponding one said plurality of word lines; means for controlling a collector-emitter voltage applied to said bipolar transistor so that the polarity of a base current changes due to impact ionization as a base-emitter voltage applied to said bipolar transistor is increased and so that a potential corresponding to a base-emitter voltage at a boundary between forward and reverse base currents is used as a writing potential; and voltage-variable means for varying an emitter voltage applied to each of said plurality of memory cells so as to set the PN junction between the base and emitter of said bipolar transistor into a forward bias state for a preset period of time at least once in a predetermined cycle. - View Dependent Claims (18, 19, 20, 21)
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Specification