Single fault/tolerant MMIC switches
First Claim
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1. A single fault/tolerant monolithic microwave integrated circuit (MMIC) for switching an RF input signal, said fault/tolerant MMIC comprising:
- a plurality of field effect transistors (FETs) including at least first, second, third and fourth FETs, each said FETs having a gate input, a source input and a drain output;
said gate inputs of said first and second FETs being coupled together and said gate inputs operating in response to a source of a first logic level to control switching of said FET;
said source inputs of said first and second FETs being connected together and adapted to receive said RF input signal;
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said drain outputs of said first and second FETs being connected together, said drain outputs of said first and second FETs each operating in response to a first logic level applied to said gate input to transmit said RF input signal whereby for a single fault of said first FET said signal FET remains operational to switch said RF input signal;
said gate inputs of said third and fourth FETs being connected to said gate inputs of said first and second FETs;
each of said first, second, third and fourth FETs include a FET having an on-resistance of approximately 50 ohms.
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Abstract
A single fault/tolerant monolithic microwave integrated circuit field effect transistor switching arrangement. This circuitry provides for the high speed (up to 18 GHz) switching of RF input signals while maintaining a circuit which is single fault/tolerant. That is, a single FET within the circuit may become faulty and the operation of the switching arrangement remains unaltered. The circuitry also provides for a self-terminating feature inherent in this FET switch.
60 Citations
13 Claims
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1. A single fault/tolerant monolithic microwave integrated circuit (MMIC) for switching an RF input signal, said fault/tolerant MMIC comprising:
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a plurality of field effect transistors (FETs) including at least first, second, third and fourth FETs, each said FETs having a gate input, a source input and a drain output; said gate inputs of said first and second FETs being coupled together and said gate inputs operating in response to a source of a first logic level to control switching of said FET; said source inputs of said first and second FETs being connected together and adapted to receive said RF input signal;
;said drain outputs of said first and second FETs being connected together, said drain outputs of said first and second FETs each operating in response to a first logic level applied to said gate input to transmit said RF input signal whereby for a single fault of said first FET said signal FET remains operational to switch said RF input signal; said gate inputs of said third and fourth FETs being connected to said gate inputs of said first and second FETs; each of said first, second, third and fourth FETs include a FET having an on-resistance of approximately 50 ohms. - View Dependent Claims (2, 3, 4, 5)
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6. A single fault/tolerant, single-pole, single-throw monolithic microwave integrated circuit (MMIC) field effect transistor (FET) switch comprising:
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an RF source for providing an input RF signal; first and second control leads for supplying first and second control signals respectively; first single fault/tolerant FET means connected to said RF source, to said first control lead and to electronic ground, said first single fault/tolerant FET means operating in response to a first logic level of said first control lead to short circuit said input RF signal to the electronic ground, said first single fault/tolerant FET means operating in response to a second logic level of said first control lead to transmit said RF input signal; second single fault/tolerant FET means connected to said first single fault/tolerant FET means, to said second control lead and to an RF output, said second single fault/tolerant FET means operating in response to said first logic level of said second control lead to transmit said input RF signal on said RF output lead, said second single fault/tolerant FET means alternately operating in response to said second logic level of said second control lead to inhibit transmission of said RF input signal on said RF output; said first single fault/tolerant FET means including a plurality of first single fault/tolerant FETs having an on-resistance of approximately 50 ohms; said second single fault/tolerant FET means including a plurality of second single fault/tolerant FETs having an on-resistance of approximately 50 ohms; and said first and said second single fault/tolerant FETs being alternately connected between said RF source and said RF output, so that there are N first single fault/tolerant FET means alternately serially connected with N-1 of said second single fault/tolerant FET means. - View Dependent Claims (7, 8)
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9. A single fault/tolerant, single-pole, double-throw MMIC FET switch comprising:
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an RF source of an RF input signal; first and second control leads for providing first and second control signals respectively; first and second RF outputs, one of said first and second outputs selectively transmitting said RF input signal; first single fault/tolerant FET switching means connected to said RF source, to said second RF output and to said first and second control leads, said first single fault/tolerant FET switching means operating in response to a first logic level of said second control lead and a second logic level of said first control lead to provide said RF input signal at said second RF output; second single fault/tolerant FET switching means connected to said RF source, said first RF output and to said first and second control leads, said second single fault/tolerant FET switching means operating in response to a first logic level of said first control lead and a second logic level of said second control lead to provide said RF input signal at said first RF output; and said first single fault/tolerant FET switching means including first and second pluralities of first single fault/tolerant FETs, each having an on-resistance of approximately 50 ohms; and said second single fault/tolerant FET switching means including first and second pluralities of second single fault/tolerant FETs, each having an on-resistance of approximately 50 ohms; said first plurality of first single fault/tolerant FETs including; first FET switching means connected to said RF source and to said second control lead; said second plurality of first single fault/tolerant FETs including; second FET switching means connected to said first FET switching means, to said first control lead and to the electronic ground; and said first plurality of first single fault/tolerant FETs further including; third FET switching means connected to said first and second FET switching means, to said second RF output and to said second control lead. - View Dependent Claims (10, 11, 12, 13)
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Specification