Layout pattern generation and geometric processing system for LSI circuits

• US 5,062,054 A
• Filed: 03/10/1989
• Issued: 10/29/1991
• Est. Priority Date: 03/10/1988
• Status: Expired due to Term

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Fukui, Masahiro, Kawakami, Yoshiyuki, Iwasaki, Chie, Shigemoto, Ichiro
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): TRANS, VINCENT N
• Application Number:
  US07/322,322
• Time in Patent Office: 963 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/112
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H05K 3/0005 for designing circuits by computer

Abstract

A printed circuit layout system using two or more of the following sub-systems: a pattern processing subsystem, a pattern design rule check subsystem, and a pattern connectivity verification characterizes any circuit pattern by a set of rectangles, each rectangle identified by a potential number and a layer, number and coordinates, and identifies terminals by potential number, layer number, and terminal names. The system eliminates the need to perform pattern OR processing and electrical connectivity search, as required by conventional schemes. The reforming and checking processes for the layout patterns are executed by a simple high speed method, making use of the features of the layout data. The system includes efficient methods for notch elimination, design rule checking, and connectivity checking.

Claims

1. A pattern processing system for laying out multi-layer LSI circuits, said layout systems comprising:

means for characterizing a circuit pattern by a set of rectangles, each rectangle being identified by a potential number, a layer number and coordinates;

means for receiving said rectangles and the design minimum spacing defined for each layer;

means for classifying said rectangles according to layer;

means for selecting any two adjacent rectangles from the classified set of rectangles for a certain layer;

means for determining whether the selected two adjacent rectangles have the same potential number;

means for determining whether the selected two adjacent rectangles are spaced further apart than the minimum spacing defined for said layer; and

means for adding a rectangle characterized by the same potential number and layer number as said two adjacent rectangles to cover the space between said selected two adjacent rectangles when their spacing is less than said design minimum spacing.

2. The pattern processing system for claim 1 further comprising:

means for determining whether said selected two adjacent rectangles overlap at any point;

means for determining whether the pattern formed by merging said selected two adjacent rectangles is still a rectangle; and

means for merging said two adjacent rectangles into one rectangle characterized by potential number, layer number and its new coordinates, said merging means creating a new merged rectangle when it is determined that the two selected rectangles overlap at some point and the pattern formed by merging them is still a rectangle.

3. A circuit pattern design rule check system comprising:

means for characterizing a circuit pattern by a set of rectangles, each rectangle being identified by a potential number, a layer number and coordinates;

means for receiving said rectangles and the design minimum spacing defined for each layer;

means for classifying said rectangle according to layer;

means for selecting any two adjacent rectangles from the classified set of rectangles for a certain layer;

means for determining whether the selected two adjacent rectangles have the same potential number;

means for determining whether the selected two adjacent rectangles are spaced further apart than the minimum spacing defined for said layer; and

means for outputting error data when the selected two adjacent rectangles are spaced further apart than said design minimum spacing for said layer.

4. A circuit pattern connectivity verification system, comprising:

means for receiving connectivity information wherein each terminal in the circuit pattern that should be connected to the same potential in said pattern is given the same net name;

means for characterizing a circuit pattern by a set of rectangles, each rectangle being identified by coordinates, a potential number and a layer number;

means for receiving layout information, including all the rectangles identified by coordinates, potential number and layer number, and all the terminals of said circuit pattern identified by coordinates, terminal name and layer number;

means for identifying the rectangles of said circuit pattern that are connected to said terminals;

means for classifying said received rectangles and said received terminals by potential number;

means for checking if the rectangles and terminals classified as having the same potential number are geometrically connected;

means for classifying said terminals by net name;

means for checking if any terminals with the same net name are in the same set classified by potential number;

means for checking if any terminals with the same potential number are in the same set classified by net name; and

means for outputting the results of said these checks.

5. A pattern layout system, comprising:

means for receiving input data including connectivity information of the circuit pattern and the location of terminals on the periphery or in the interior of said pattern;

means for generating output data characterizing said pattern by rectangles identified by coordinates, potential number and layer number, and identifying the terminals by coordinates, terminal name and layer number;

modifying the output data from said generating means to delete undesirable notches and slits;

means for checking to determine if the output data from said generating means conforms to the design rules of the pattern being laid out; and

means for checking to determine if the output data from said generating means satisfies the requirements of the input data received by said receiving means.

6. The pattern layout system of claim 5 further comprising means for manually changing the output data from said generating means.

7. A pattern processing system for laying out multi-layer LSI circuits, said layout system comprising:

means for characterizing a circuit pattern by a set of rectangles, each rectangle being identified by a potential number, a layer number, and coordinates;

means for receiving said rectangles and the design minimum spacing defined for each layer;

means for classifying said rectangles according to layer;

means for selecting any two adjacent rectangles from said classified set of rectangles;

means for determining whether the selected two adjacent rectangles have the same potential number;

means for determining whether the pattern formed by merging said two rectangles is still a rectangle; and

means for merging the two adjacent rectangles into one rectangle, characterized by the same potential number and layer number as said two rectangles but with new coordinates, wherein said merging means creates a new merged rectangle when it is determined that the two selected rectangles overlap at some point and the pattern formed by merging them is still a rectangle.

8. A circuit pattern design rule check system, for checking the condition that a rectangle on one layer "A" is included by a rectangle on another layer "B" when the rectangle on layer "B" is expanded in all directions by a distance "W," said check system comprising:

means for characterizing a circuit pattern by a st of rectangles, each rectangle being identified by a potential number, a layer number, and coordinates;

means for receiving said rectangles and the design minimum spacing defined for each layer;

means for classifying said rectangles according to layer;

means for checking whether a rectangle on layer "B," when expanded in all directions by said distance "W," includes a rectangle on said layer "A"; and

means for outputting error data as the result of said check.