Computer display controller with reconfigurable frame buffer memory

• US 5,062,057 A
• Filed: 12/09/1988
• Issued: 10/29/1991
• Est. Priority Date: 12/09/1988
• Status: Expired due to Term

• Current Assignee: Autodesk, Inc.
• Original Assignee: E-Machines Incorporated
• Inventors: Berry, James D., Blacken, Laurin G.
• Primary Examiner(s): Herndon, Heather R.
• Application Number:
  US07/282,472
• Time in Patent Office: 1,054 Days
• Field of Search: 364/518, 364/521, 340/721, 340/723, 340/747, 340/798, 340/799, 340/800
• US Class Current: 345/567
• CPC Class Codes: G09G 5/346 for systems having a bit-mapped display memory
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A computer display controller (50) cooperates with a host microprocessor (18) to direct display data to a frame buffer memory (16) in accordance with a selected one of multiple frame buffer memory configurations (20 and 30). The display controller includes an address decoder circuit (58) that delivers address information generated by the host microprocessor to the address inputs (64) of the frame buffer memory in accordance with the selected frame buffer memory configuration.

Claims

1. A computer display controller in communication with a frame buffer memory having plural address locations to which display data are directed in accordance with address information provided by a host microprocessor, comprising:

format storage means for storing address format information corresponding to an address information arrangement for each of plural frame buffer memory configurations representing different arrangements of the address locations in the frame buffer memory; and

address decoding means receiving the address information provided by the host microprocessor and receiving the format information corresponding to a selected one of the frame buffer memory configurations for delivering to the frame buffer memory the address information arranged in accordance with the selected one of the frame buffer memory configurations.

2. The controller of claim 1 in which each of the plural frame buffer memory configurations includes substantially all of the address locations in the frame buffer memory.

3. The controller of claim 1 in which the display data represent selected ones of multiple pixels arranged in a first array of rows and columns on a display screen and in which each frame buffer memory configuration represents a second array of rows and columns of address locations, whereby there is a one-to-one correspondence between the rows and columns of pixels on the display screen and selected ones of the rows and columns of address locations in each frame buffer memory configuration.

4. The controller of claim 3 in which different ones of the plural frame buffer memory configurations include different numbers of rows and columns of address locations.

5. The controller of claim 1 in which each frame buffer memory configuration represents an array of rows and columns of address locations.

6. The controller of claim 5 in which the multiplicative product of the number of rows and the number of columns in each of the plural frame buffer memory configurations is substantially equal to a preselected value.

7. The controller of claim 6 in which the preselected value represents the number of address locations in the frame buffer memory.

8. The controller of claim 5 in which the address information generated by the host microprocessor is delivered to the address decoding means as N number of digital bits corresponding to the number of rows of address locations and M number of digital bits corresponding to the number of columns of address locations.

9. The controller of claim 8 in which different ones of the plural frame buffer memory configurations employ different numerical values for the numbers N and M and in which the sum of the numbers N and M is equal to a preselected value for each one of the frame buffer memory configurations.

10. The controller of claim 1 in which the address decoding means includes a programmable logic array.

11. In a computer system having a host microprocessor that generates display data representing selected ones of a first set of pixels arranged in a first array of rows and columns on a display screen, the host microprocessor directing the display data to address locations within a frame buffer memory in accordance with address information, a display controller that communicates with the host microprocessor and the frame buffer memory, comprising:

frame buffer memory configuration means for arranging the address information corresponding to substantially all of the address locations in the frame buffer memory in accordance with a selected one of plural frame buffer memory configurations; and

means for forming from each frame buffer memory configuration a corresponding display space representing a second set of pixels arranged in a second array of rows and columns, whereby the rows and columns in the first array on the display screen correspond to selected ones of the rows and columns in the second array in the display space.

12. The controller of claim 11 in which the number of rows in the second array is greater than the number of rows in the first array and the controller further includes row assigning means for assigning the rows of the first array to different selected ones of the rows of the second array.

13. The controller of claim 12 in which the rows of the first and second arrays correspond to a vertical direction on the display screen, whereby the assigning means functions to achieve a panning of the display screen across the display space in a vertical direction.

14. The controller of claim 12 in which the number of columns in the second array is greater than the number of columns in the first array and the controller further includes column assigning means for assigning the columns of the first array to different selected ones of the columns of the second array.

15. The controller of claim 14 in which the rows of the first and second arrays correspond to a vertical direction on the display screen and the columns of the first and second arrays correspond to a horizontal direction on the display screen, whereby the row assigning means and the column assigning means function to achieve panning of the display screen across the display space in a vertical direction and a horizontal direction, respectively.

16. The controller of claim 11 in which the frame buffer memory includes plural memory locations each of which is identified by a corresponding one of the plural address locations and in which the frame buffer memory configuration means provides for each frame buffer memory configuration a number of address locations that is greater than the number of memory locations.

17. The controller of claim 11 in which the frame buffer memory configuration means arranges the address locations for each frame buffer memory configuration in a third array of rows and columns and in which each row of each frame buffer memory configuration includes a first set of address locations that have corresponding memory locations and a second set of address locations that do not have corresponding memory locations.

18. The controller of claim 17 in which the frame buffer memory configuration means provides for substantially all of the rows of address locations in a frame buffer memory configuration first and second preselected numbers of address locations in the respective first and second sets of address locations and in which the values of the first and second preselected numbers for each frame buffer memory configuration are different.

19. The controller of claim 18 in which the ratio of the first and second preselected numbers for each frame buffer memory configuration is equal to a third preselected number.