Delay-locked loop circuit in spread spectrum receiver
First Claim
1. Spread spectrum receiver including a terminal for a received spread spectrum signal and a delay locked loop circuit for holding the synchronization of a despread signal with the received spread spectrum signal, the circuit comprising:
- a voltage control oscillator for generating a clock signal;
a despread signal generator controlled by said clock signal for generating a first despread signal and second despread signal, the first despread signal being shifted in phase by one bit to the second despread signal;
first correlation means for producing a first signal representative of a correlation of the received spread spectrum signal with the first despread signal;
second correlation means for generating a second signal representative of a correlation of the received spread spectrum signal with the second despread signal;
a subtracter for generating a signal representative of a subtraction between said first and second correlation representative signals;
a positive feedback amplifier for amplifying said subtraction representative signal which is applied to said voltage control oscillator as a control signal; and
a window comparator with a predetermined window width for in response to the subtraction representative signal for producing a lock signal when the subtraction representative signal is positioned within the window width and an unlock signal when outside the window width.
2 Assignments
0 Petitions
Accused Products
Abstract
Spread spectrum receiver includes a delay locked loop (DLL) circuit for holding the synchronization of a despread signal with a received spread spectrum signal. The DLL circuit comprises a subtracter for generating a signal representative of a subtraction between first and second correlation signals, a positive feedback amplifier for amplifying the subtraction representative signal and a window comparator for producing a lock signal when the subtraction representative signal is positioned within a window width.
-
Citations
12 Claims
-
1. Spread spectrum receiver including a terminal for a received spread spectrum signal and a delay locked loop circuit for holding the synchronization of a despread signal with the received spread spectrum signal, the circuit comprising:
-
a voltage control oscillator for generating a clock signal; a despread signal generator controlled by said clock signal for generating a first despread signal and second despread signal, the first despread signal being shifted in phase by one bit to the second despread signal; first correlation means for producing a first signal representative of a correlation of the received spread spectrum signal with the first despread signal; second correlation means for generating a second signal representative of a correlation of the received spread spectrum signal with the second despread signal; a subtracter for generating a signal representative of a subtraction between said first and second correlation representative signals; a positive feedback amplifier for amplifying said subtraction representative signal which is applied to said voltage control oscillator as a control signal; and a window comparator with a predetermined window width for in response to the subtraction representative signal for producing a lock signal when the subtraction representative signal is positioned within the window width and an unlock signal when outside the window width. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. A spread spectrum receiver comprising:
-
a terminal for receiving a spread spectrum signal; means (213) for generating a despread signal; means (201-212) for producing a synchronization signal derived from the synchronization status of the despread signal with the received spread spectrum signal; means (215-218) for forming a lock signal when the synchronization signal is within a predetermined range and unlock signal where the synchronization signal outside the predetermined range; and means (219, 220,
221) for setting a first width for the predetermined range in response to the lock signal and a second width in response to the unlock signal, the first width being wider than the second width. - View Dependent Claims (8, 9, 10, 11, 12)
-
Specification