Insulated gate transistor devices with temperature and current sensor

• US 5,063,307 A
• Filed: 09/20/1990
• Issued: 11/05/1991
• Est. Priority Date: 09/20/1990
• Status: Expired due to Term

• Current Assignee: Mercury Interactive Corp. (HP Inc.)
• Original Assignee: IXYS Corporation (Littelfuse Incorporated)
• Inventors: Zommer, Nathan
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): Tran, Sinh N.
• Application Number:
  US07/585,847
• Time in Patent Office: 411 Days
• Field of Search: 307/310, 307/362, 328/3, 323/313, 323/314, 323/289, 374/178, 357/28
• US Class Current: 327/512
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 29/7815 with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 17/0822 in field-effect transistor switches
• CPC Class Codes: H03K 17/567 Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
• CPC Class Codes: H03K 2017/0806 against excessive temperature

Abstract

A technique for sensing the temperature of power MOS devices contemplates a main transistor and monolithically formed sense transistor. A resistor, which may integrated into the device or may be off chip, is connected between the respective source nodes of the main transistor and the sense transistor (as in a normal current mirror). However, the respective gate nodes of the main transistor and the sense transistor are not directly connected to each other (in contrast to the normal current mirror configuration where the respective gate nodes of the main transistor and the sense transistor are directly connected). Rather, the sense transistor gate node is coupled to the output terminal of an operational amplifier. The amplifier, has a first input terminal coupled to a reference voltage and a second, complementary, input terminal coupled to the sense transistor source node.

Claims

1. A semiconductor device in combination with temperature sensing circuitry comprising:

a first insulated gate transistor having a first drain node, a first gate node, and a first source node;

a second insulated gate transistor, monolithic with and much smaller than said first transistor, having a second drain node, a second gate node, and a second source node;

said first and second drain nodes having a common connection;

a resistor coupled between said first and second source nodes;

means defining a reference voltage; and

an operational amplifier having a first input terminal coupled to said reference voltage, a second complementary input terminal coupled to said second source node, and an output terminal coupled to said second gate node;

whereupon when current flows from said second drain node, through said second gate insulated transistor, through said resistor, and to said second source node, the voltage appearing at said second gate terminal provides a direct measure of the temperature of said second insulated gate transistor.

2. The combination device of claim 1 wherein said first and second insulated gate transistors are MOSFETs.

3. The combination device of claim 1 wherein said first and second insulated gate transistors are IGBTs.

4. The combination of claim 1, and further comprising switching means for disconnecting said operational amplifier'"'"'s output terminal from said second gate node and for connecting said second to said first gate node, whereby the voltage appearing across said resistor provides a representation of the current flowing through the device.

5. The combination of claim 1 wherein said first and second insulated gate transistors are n-channel enhancement mode devices.

6. The combination of claim 1 wherein said resistor is formed monolithically with said first and second insulated gate transistors.