Radar warning receiver compressed memory histogrammer

• US 5,063,385 A
• Filed: 04/12/1991
• Issued: 11/05/1991
• Est. Priority Date: 04/12/1991
• Status: Expired due to Fees

• Current Assignee: United States Of America As Represented By The Secretary Of The Air Force
• Original Assignee: United States Of America As Represented By The Secretary Of The Air Force
• Inventors: Caschera, Joseph
• Primary Examiner(s): Sotomayor, John B.
• Application Number:
  US07/684,074
• Time in Patent Office: 207 Days
• Field of Search: 342/13, 342/14, 342/15, 342/20
• US Class Current: 342/13
• CPC Class Codes: G01S 7/021 Auxiliary means for detecting or identifying radar signals or the like, e.g. radar jamming signals

Abstract

A memory system for histogramming the pulse descriptor word output of a radar warning receiver for initial processing of the received data for quickly determining the numbers and types of emitters in the system'"'"'s environment. The disclosed apparatus histograms the number of pulses received in a given time interval versus scaled values of frequency and time differences of arrival plus it assigns available memory locations only when confirmed data is received. A typical histogram size of 1,024 (radio frequency) by 8,192 (time difference of arrival), or 8,388,608 pixels is disclosed along with comparisons and contrasts with less efficient conventional histogramming arrangements.

Claims

1. A method for preserving radar warning receiver generated pulse descriptor words for subsequent histogram organized processing comprising the steps of:

initializing each location of a frequency characterizing pulse descriptor word portion first memory and a time difference of arrival second memory to flag bit active predetermined initial condition;

storing, in a location of said first memory accessed by the frequency characterizing portion of an arriving pulse descriptor word from said receiver, the current contents of a first counter circuit;

remembering the time of arrival of said pulse descriptor word in a last time of arrival third memory;

incrementing the contents of said first counter circuit by one count;

computing the time difference of arrival value between each new pulse descriptor word arriving from said receiver and the remembered time of arrival stored in said third memory;

said storing, remembering, and computing steps being inhibited and said computing step enabled, however, by prior deactivation of said flag bit in said first memory accessed location;

addressing a location in said time difference of arrival second memory with said computed time difference of arrival value;

testing said addressed second memory location for presence for said second memory predetermined initial flag bit active condition therein;

setting the contents of said addressed second memory location to the present contents of a second counter circuit;

indexing the contents of said second counter circuit by one count;

said setting and indexing step being inhibited, however, by prior deactivation of said flag bit in said addressed second memory location;

accessing a histogram organized fourth memory location by the combined stored data from said first and second;

testing said accessed fourth memory location for an initial volume of zero;

incrementing said accessed fourth memory location by one;

if initial state of said accessed fourth memory location prior to incrementing is zero;

recording in an active pixel fifth memory, in the first available location therein, the address parameters and the most recently stored values from said frequency characterization first memory and said time difference of arrival second memory;

whereby active only pixel storage and reduced memory size requirements for said active pixel fifth memory are achieved.

2. The method of claim 1 wherein the steps from said step of initializing through said step of incrementing end upon overflowing of said first counter.

3. The method of claim 1 wherein said steps of computing through incrementing end upon overflow of said second counter.

4. The method of claim 1 wherein said steps of initialing through incrementing and said step of computing through incrementing end with expiration of a data collection period.

5. The method of claim 1 wherein said first and second memory flag bits comprise higher ordered memory word bits and said flag bits are excluded from being set by data received in said memories.

6. The method of claim 1 wherein said combined first and second memory stored data includes a first predetermined number of data bits from said first memory and a second greater predetermined number of data bits from said second memory.

7. The method of claim 1 further including the steps of reading said warning receiver data from said active pixel memory during a sequential accessing of said memory.

8. The method of claim 7 further including the memory to processor data communication steps of:

sequentially accessing the data located in said active pixel fifth memory to obtain a sequence of pixel address and histogram address data words;

accessing the location in said time difference of arrival second memory and said histogram fourth memory using the histogram address contents of said accessed active pixel fifth memory data words as addresses;

communicating the pixel address data read from said fifth memory location to said processor;

transferring the contents of the accessed histogram memory location to said processor;

resetting said accessed time difference of arrival second memory words to said preset flag bit active condition;

clearing each said accessed histogram fourth memory location to the zero condition.

9. The method of claim 8 wherein said data communicating steps are limited to one sequence of sequentially accessing through clearing sequence for each active pixel.

10. The method of claim 8 further including the steps of clearing said last time of arrival third memory and said frequency characterizing first memory and presetting said flap bit predetermined conditions in said first memory.

11. Memory apparatus for efficiently capturing in histogram array the pulse data word output signals of a radar warning receiver comprising the combination of:

first digital counter means for incrementally accumulating the number of pulse descriptor words received from said warning receiver;

first memory means addressed by the frequency characteristic portion of a pulse descriptor word received from said warning receiver for conditionally storing the present contents of said first digital counter means;

third memory means for conditionally remembering the time of arrival of a pulse descriptor word from said warning receiver;

computation means for determining time difference of arrival values between a current pulse descriptor word and said third memory means stored pulse descriptor word time of arrival;

second digital counter means for conditionally incrementally accumulating the number of pulse descriptor words of identical radio frequency characteristic receive from said warning receiver;

second memory means addressed by said computed time difference of arrival for conditionally storing the incrementally accumulated present value in said second digital counter means;

histogram amplitude fourth memory means including memory locations addressable by data word combinations from said first and second memory means for counting in each respective addressed location thereof, the number of first memory means and second memory means identified pulse descriptor words located in a related histogram map cell,

fifth active pixel memory means for sequentially storing the frequency characteristic and time difference of arrival componented histogram pixel address words and histogram amplitude address words for each active pixel in said histogram map.

12. The memory apparatus of claim 11 further-. including:

initial conditioning means responsive to a power up signal for presetting a flag bit in each location of said first memory means,

means responsive to the undisturbed presence of said preset flag bit in said first memory means addressed location for enabling said conditional storage of said first digital counter means present value in said first memory means and subsequent incrementing of said first digital means;

means responsive to the absence of said preset flag bit for enabling said conditional time difference of arrival remembering in said second memory means.

13. The memory apparatus of claim 12 further including

initial conditioning means responsive to a power up signal for presetting a flag bit in each location of said second memory means;

means responsive to the undisturbed presence of said preset flag bit in said second memory means addressed location for enabling said conditional storage of said second digital counter means present value in said second memory means and subsequent incrementing of second digital counter means;

means responsive to the undisturbed presence of said preset flag bit in said second memory means addressed location for enabling said conditioned incrementing of said histogram amplitude fourth memory.

14. The memory apparatus of claim 13 further including:

means for sequentially accessing the data located in said active pixel fifth memory means to obtain a sequence of histogram pixel address and histogram amplitude address data words therefrom;

means for reading into said processor the histogram pixel address data in said active pixel fifth memory and also said histogram amplitude fourth memory means data words, using said accessed fifth memory means histogram amplitude memory address data as addressed.