Programmable data communications controller

• US 5,063,494 A
• Filed: 04/12/1989
• Issued: 11/05/1991
• Est. Priority Date: 04/12/1989
• Status: Expired due to Term

• Current Assignee: Unisys Corporation Township Line and Union Meeting Road Blue Bell PA 19424
• Original Assignee: Unisys Corporation
• Inventors: Davidowski, Dennis J., Saunders, Michael J., O'Brien, Steven M.
• Primary Examiner(s): Chan, Eddie P.
• Application Number:
  US07/336,980
• Time in Patent Office: 937 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 709/246
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

The present invention provides a novel programmable data communications controller employed to accept data from a host computing system and for transmitting the data to a terminal designated by the host computer system. The data computer communications controller is further provided with protocols, parameters and poll tables stored in a dedicated memory of the data communications controller which enables the controller to receive data and address information from a main memory of a host computer and to reformat and pre-package the information in a protocol format block acceptable by a terminal coupled to the data communications controller. Different protocols, parameters and polls are provided in the data communications controller in the form of preprogrammed information which enables different terminals employing different protocols and protocol formats to be coupled directly to a data link interface bus without hardware modifications. Different protocols are loaded into the main memory of the main computer system and down loaded into the bit map memory of the data communications controller upon initialization of the system.

Claims

1. A high speed external data communications controller for receiving data from a main memory to be transferred to a smart terminal, comprising:

a host computer system comprising an input/output control processor coupled to a main memory through a common system bus means,

said main memory having data stored therein to be transmitted to a smart terminal,

an input/output adapter coupled between said common system bus means and a common data link interface bus,

a plurality of smart terminals coupled to said common data link interface bus,

an enhanced data communications data link processor (EDC DLP) of the type having a programmable microprocessor and a dedicated memory, for storing protocols, terminal configurations and other parameters defining the data communications system said EDC DLP being coupled between said smart terminals and said data link interface bus,

said EDC DLP providing means for receiving information from said main memory of said host computer including data and a designated smart terminal address for receiving said data in a format unacceptable by said designated smart terminal,

said dedicated memory providing means for storing said received data,

said EDC DLP further providing means for utilizing the information stored in said dedicated memory and for formatting and pre-packaging said received data in a format acceptable by said smart terminal,

said formatted pre-packaged data including a plurality of prefix code characters and a suffix code character, and

means for transmitting said pre-packaged acceptable format text to said designated smart terminal.

2. A high speed data communications controller as set forth in claim 1 wherein said EDC DLP further provides means for polling said designated terminal.

3. A high speed data communications controller as set forth in claim 1 wherein said pre-packaged data for polling a terminal comprises the characters:

SYNC, start of header, address, followed by acknowledge, end of text and a block check character.

4. A high speed data communications controller as set forth in claim 3 wherein said block check character provides means for checking proper transmission of said address for polling.

5. A high speed data communications controller for receiving data from a smart terminal to be transferred to user equipment in a computing system, comprising:

an input/output adapter coupled between a common data link interface bus and a common system bus means connected to a main processor system having an input/output control processor and a main memory,

a plurality of smart terminals,

enhanced data communications data link processor means (EDC DLP) connected between said plurality of smart terminals and said data link interface bus,

said EDC DLP having a programmable microprocessor and a dedicated memory for storing protocols terminal configurations and other parameters defining the data communications system and for receiving data from smart terminals to be transferred to any other device memory in said computing system,

said EDC DLP providing means for receiving information from said main memory including data and a designated device address for receiving said data in a format unacceptable by said designated device,

said dedicated memory providing means for receiving said data and an address from a smart terminal,

said EDC DLP further providing means for utilizing the information stored in said dedicated memory and for formatting and pre-packaging said received data and address in a format acceptable to said designated device,

said formatted pre-packaged data further including a plurality of prefix code characters and a suffix code character, and

means for polling said smart terminal to elicit transmission of said information including data and a designated device address for receiving said data.

6. A high speed data communications controller as set forth in claim 5 wherein said EDC DLP further comprises means for receiving data and a device memory address from a smart terminal in response to a first poll.

7. A high speed data communications controller as set forth in claim 6 which further includes means for prepackaging and generating a second poll in response to receiving said data and a device address from a smart terminal.

8. A high speed data communications controller as set forth in claim 7 wherein said second poll comprises the characters:

SYNC, start of header, address, followed by acknowledge, end of text and a block check character.