Channelized delay and mix chip rate detector

• US 5,063,572 A
• Filed: 06/04/1990
• Issued: 11/05/1991
• Est. Priority Date: 06/04/1990
• Status: Expired due to Fees

• Current Assignee: L-3 Communications Corporation (L3Harris Technologies, Inc.)
• Original Assignee: Unisys Corporation
• Inventors: Smith, Patrick J., Leahy, Ronald S.
• Primary Examiner(s): TARCZA, THOMAS H
• Application Number:
  US07/533,183
• Time in Patent Office: 519 Days
• Field of Search: 375/1, 350/356
• US Class Current: 375/131
• CPC Class Codes: H04B 1/692 Hybrid techniques using combinations of two or more spread spectrum techniques
• CPC Class Codes: H04K 3/228 Elimination in the received signal of jamming or of data corrupted by jamming interference suppression in receivers H04B1/10

Abstract

A detector circuit for indicating the chip rate of a direct sequence frequency hopped data transmission signal. The wide band input signal is channelized into L adjacent sub-bands and each sub-band signal is multiplied by a delayed copy of itself and then hard limited, after which all the hard limited product signals are totalized to give a resultant signal representative of the chip rate.

Claims

1. A chip rate detector for detection of the chip rate of coded bits of a direct sequence frequency hopped input signal comprising:

(a) channelizing means having sections for splitting said input signal for transmission into L separate sub-bands of frequency ranges;

(b) delay means, in each sub-band of said channelizing means for delaying said sub-band signal by a fixed constant to obtain a delayed sub-band signal;

(c) mixing means for multiplying said delayed sub-band signal with said sub-band signal to provide a sub-band product signal;

(d) summation means for totalizing the sum of each sub-band product signal to generate a final output chip rate signal.

2. The detector of claim 1 wherein said mixing means includes:

(a) threshold means for applying a pre-set limit to each one of said sub-band product signals.

3. The detector of claim 1 which includes:

(a) spectral analysis means using said final output signal to generate a display of the chip rate frequency component detected.

4. A chip rate detector apparatus comprising:

(a) means for channelizing a direct sequence frequency hopped input signal into L separate sub-bands to provide diminished bandwidth signals for each separate sub-band wherein each one of said L sub-bands includes;

(a1) delay and mix detector means for providing a copy of said sub-band signal, which has been delayed by approximately one-half the direct sequence chip dwell period, to a multiplier means;

(a2) said multiplier means for multiplying said delayed sub band signal by the original sub-band signal to develop a product output signal;

(b) summation circuit means for summing the product output signals from each of said L sub-bands and including;

(b1) a final output signal with a frequency component corresponding to the chip rate of said direct sequence frequency hopped input signal.

5. The apparatus of claim 4 which includes:

(a) spectrum analyzer means for displaying the said chip rate frequency component for visual observation.

6. A chip rate detector for direct sequence frequency hopped data transmission signals operating over a selected bandwidth comprising:

(a) means for receiving said data transmission as an input signal having a chip rate of R_c ;

(b) means for separating said input signal into L sub-bands to provide L independent signals;

(c) means for delaying each of said L independent signals by approximately one-half of the direct sequence dwell time, T_c, and multiplying each delayed independent signal by its corresponding original signal to generate a sub-band product signal;

(d) threshold limiting means for applying a preset limit to each of said sub-band product signals;

(e) summation means for totalizing all of said L sub-band product signals to develop a final output signal containing a harmonic at the chip rate R_c of the said original input signal.

7. The detector of claim 6 wherein said means for separating said input signal includes:

(a) a plurality of L band pass filters where each filter operates to pass a limited portion W/L of the bandwidth W, where W is the overall bandwidth of the frequency hopped input signal.

8. The detector of claim 6 wherein said means for delaying includes:

(a) adjustable delay-line circuit means.

9. The detector of claim 6 wherein said threshold limiting means is provided with a pre-set limiting value of L_th for each sub-band signal so as to limit the influence of any unwanted interference signals occurring in that sub-band.

10. A chip rate detector for indicating the chip rate R_c of a direct sequence frequency hopped input signal comprising:

(a) means for channelizing said input signal into sectionalized bandwidth signals;

(b) means for delaying, for a pre-set delay time, each of said sectionalized bandwidth signals;

(c) means for multiplying each said original sectionalized bandwidth signal by said delayed sectionalized bandwidth signal to generate a sectionalized bandwidth product signal;

(d) means for limiting each of said sectionalized bandwidth product signals by quantizing to a binary level value;

(e) means for totalizing the sum of all of said limited and sectionalized bandwidth product signals to generate a final output result signal representative of said chip rate, R_c.

11. A chip rate (R_c) detector for direct sequence frequency hopped input signals comprising:

(a) means for channelizing said input signal into L sub-bands of width W/L where W is the input signal bandwidth and L is the number of sub-bands;

(b) means for delaying each sub-band signal by T_c /2 and multiplying said delayed signal by the original sub-band signal to develop a sub-band product signal;

(c) means for limiting the amplitude of each sub-band product signal with a predetermined threshold;

(d) means to add all of said sub-band product signals to generate a final result signal which indicates the chip rate, R_c.