Fabrication method for a double trench memory cell device

• US 5,064,777 A
• Filed: 03/04/1991
• Issued: 11/12/1991
• Est. Priority Date: 06/28/1990
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dhong, San H., Hwang, Wei
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Thomas, Tom
• Application Number:
  US07/664,684
• Time in Patent Office: 253 Days
• Field of Search: 437/38, 437/97, 437/48, 437/51, 437/52, 437/60, 437/191, 437/193, 437/195, 437/200, 437/203, 437/228, 437/233, 437/235, 437/919, 357/23.6, 357/51
• US Class Current: 438/242
• CPC Class Codes: H01L 29/945 Trench capacitors
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

A method is described for fabricating a novel double trench memory structure including a shallow trench access transistor adjacent to a deep trench storage capacitor. The described three-dimensional DRAM cell structure consists of shallow trench access transistors and deep trench storage capacitors in a n-well disposed on a semiconductor substrate. In the fabrication method, the vertical access transistors are built adjacent to the one side of one deep substrate-plate trench storage capacitor. Arrangement of the access transistors and trench storage capacitor are different from that of standard single trench cells. The layout of the double trench cell not only provides the advantages of small size, high packing density, lower soft error rate, and higher noise immunity for storage capacitor, but also leads to better performance and an efficient sensing scheme. The structure may be fabricated for p-channel or n-channel embodiments.

Claims

1. A method for fabricating a double trench semiconductor memory storage structure comprising the steps of:

Step 1. forming a first trench having bottom and side walls in a semiconductor substrate including first conductivity epitaxial layer disposed on a silicon layer,

Step 2. forming a layer of dielectric insulating material on said bottom and side walls of said first trench to provide a storage capacitor insulator,

Step 3. implanting second conductivity dopants opposite to said first conductivity in said epitaxial layer to form a well region,

Step 4. filling said first trench with conductive material to provide a storage capacitor plate element,

Step 5. forming a second trench having bottom and side walls in said well region adjacent to and partially disposed in a portion of said first trench filled with said conductive material

Step 6. forming a layer of dielectric insulation on said bottom and side walls of said second trench,

Step 7. filling said second trench with conductive material to form a vertical access transistor device transfer gate and word line,

Step 8. forming a junction in said well region adjacent to said second trench to provide a vertical access transistor source element,

Step 9. forming a junction in said well region adjacent to said first and second trench to provide a vertical access transistor drain element.

2. A method of fabricating a double trench semiconductor memory storage structure according to claim 1 further including the steps of:

Step 10. forming a layer of electrical insulating material over said epitaxial layer with an access opening therein to said source element.

Step 11. forming a layer of conductive material over said insulating material formed in Step 10 to provide a bit line wherein said conductive material fills said access opening to contact said source element.

3. A method for fabricating a double trench semiconductor memory storage structure according to claim 1 wherein in Step 1 said substrate includes p-conductivity epitaxial layer on a p+ silicon layer and in Step 3 n+ conductivity dopants are implanted in said epitaxial layer to form a well region.

4. A method for fabricating a double trench semiconductor memory storage structure according to claim 1 wherein Step 7 includes filling said shallow trench with CVD p+ polysilicon and chem-mech polishing and patterning to form said transfer gate and word lines.

5. A method for fabricating a double trench semiconductor memory storage structure according to claim 1 wherein said Step 5 includes the step of etching a shallow trench in the n-well regions by RIE to form vertical access transistor region and Step 6 includes the steps of growing a thin selective epi-layer along the inside of said shallow trench, growing thin pad oxide, chemically depositing a silicon nitride layer over the shallow trench and the surface of the substrate, and forming silicon nitride side wall spacers by reactive ion etching the said nitride.

6. A method for fabricating a double trench semiconductor memory storage structure according to claim 5 wherein Step 6 further includes the steps of growing regions of thicker oxide over the said storage capacitor material node and said drain junction simultaneously for reducing coupling capacitances within said memory storage structure.

7. A method for fabricating a double trench semiconductor memory storage structure according to claim 1 wherein Steps 8 and 9 include implanting p-type dopants through the said layer on the surface of said shallow trench and said n-well layer to form p+ source and p+ drain junctions.

8. A method for fabricating a double trench semiconductor memory storage structure according to claim 7 wherein the threshold voltage of said vertical access trench transistor is selectively adjusted by using an oblique angle ion implantation technique.