Programmable resistor and an array of the same

• US 5,065,132 A
• Filed: 11/16/1990
• Issued: 11/12/1991
• Est. Priority Date: 11/16/1990
• Status: Expired due to Fees

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Shichijo, Hisashi, Taddiken, Albert H., Yuan, Han-Tzong
• Primary Examiner(s): Lateef, Marvin M.
• Application Number:
  US07/614,473
• Time in Patent Office: 361 Days
• Field of Search: 338/334, 338/306, 338/308, 338/195, 338/48, 338/307, 307/201, 307/264, 307/490, 323/354, 364/482, 29/610.1, 437/918, 357/51
• US Class Current: 338/334
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: G11C 11/34 using semiconductor devices
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 27/00 Electric analogue stores, e.g. for storing instantaneous values
• CPC Class Codes: H01C 13/00 Resistors not provided for elsewhere
• CPC Class Codes: H01L 29/7832 the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
• CPC Class Codes: H01L 29/8124 with multiple gate

Abstract

A programmable resistor 10 is provided having a resistive element 12. Resistive element 12 includes a substrate 26 formed by a layer of semiconductor of a first conductivity-type. A current path 32 is formed in substrate 26 by a layer of semiconductor of a second conductivity-type. An interface 36 having interfacial traps is formed between current path 32 and substrate 26. A backgate 24 is formed adjacent substrate 26. A first switch 14 selectively couples backgate 24 to a first voltage while a second switch 16 selectively couples backgate 24 to a second voltage.

Claims

1. A programmable resistor, comprising:

a substrate formed of a layer of semiconductor of a first type;

a current path region of a second type formed in said substrate wherein an interface having interfacial traps is formed between said current path and said substrate;

a backgate formed adjacent said current path; and

circuitry coupled to said backgate for varying the number of carriers residing in said interfacial traps.

2. The programmable resistor of claim 1, wherein said current path comprises a channel area of a field effect transistor.

3. The programmable resistor of claim 2, wherein said field effect transistor comprises a metal semiconductor field effect transistor.

4. The programmable resistor of claim 2, wherein said field effect transistor comprises a metal oxide semiconductor field effect transistor.

5. A programmable resistor, comprising:

a field effect transistor including a channel area formed in a layer of semiconductor so as to create a plurality of interfacial traps along an interface between the channel and the layer of semiconductor;

a backgate spaced from said channel area operable to vary the resistance of the channel area responsive to a voltage applied thereto;

a first switch selectively coupling said backgate to a first voltage source; and

a second switch selectively coupling said backgate to a second voltage source.

6. The programmable resistor of claim 5, wherein said layer of semiconductor is of a first type and said channel area is of a second type formed therein.

7. The programmable resistor of claim 5, wherein said first switch couples said backgate to a positive voltage and said second switch couples said backgate to a negative voltage.

8. The programmable resistor of claim 5, wherein said channel area is formed of N type gallium arsenide and said layer of semiconductor is formed of semi-insulating gallium arsenide.

9. The programmable resistor of claim 5, wherein said channel area is formed of N type silicon and said layer of semiconductor is formed of P type silicon.

10. The programmable resistor of claim 5, wherein said channel is formed of P type silicon and said layer of semiconductor is formed of N type silicon.

11. The programmable resistor of claim 5, wherein said channel area is formed of P type gallium arsenide and said layer of semiconductor is formed of semi-insulating gallium arsenide.

12. A programmable resistor, comprising:

a field effect transistor formed in a semiconductor substrate of a first type conductivity comprising;

a source region of a second conductivity type formed in said substrate;

a drain region of said second conductivity type formed adjacent said substrate;

a channel area of said second conductivity type formed adjacent said substrate, such that an interface having interfacial traps with said substrate is formed therebetween; and

a gate formed adjacent to said channel area;

a backgate spaced from said channel area and formed adjacent said substrate to be of said second conductivity type such that the resistance of the channel area can be varied responsive to a voltage applied to the backgate;

a first switch selectively connecting said backgate to a first voltage; and

a second switch selectively connecting said backgate to a second voltage.

13. The programmable resistor of claim 12, wherein said gate comprises a Schottky barrier gate.

14. The programmable resistor of claim 12, wherein said gate is separated from said channel area by a layer of insulator.

15. The programmable resistor of claim 12, wherein said source and drain regions and said backgate comprise heavily doped diffused regions of said second conductivity type and said channel area comprises a lightly doped diffused region of said second conductivity type.

16. The programmable resistor of claim 15, wherein said source and drain regions and said backgate comprise n+regions and said channel area comprises an n-area.

17. The programmable resistor of claim 12 and further comprising an isolation region formed in said layer of semiconductor and laterally enclosing at least said field effect transistor and said backgate.

18. The programmable resistor of claim 17 wherein said isolation region comprises an electrically biased conductive region.

19. The programmable resistor of claim 17 and further comprising a thick insulator layer overlying said isolation region.

20. The programmable resistor of claim 19 wherein said thick insulator layer comprises a layer of thick oxide.

21. A neural network array comprising:

a plurality of input lines;

a plurality of output lines;

a plurality of programmable resistors coupling each of said input lines with each of said output lines, said programmable resistors comprising;

a substrate formed of a layer of semiconductor of a first type;

a current path region of a second type formed in said substrate wherein an interface having interfacial traps is formed between said current path and said substrate;

a backgate formed adjacent said current path; and

circuitry coupled to said backgate for varying the number of carriers residing in said interfacial traps.

23. The method of claim 21, wherein said step of increasing the resistance of the current path comprises the step of applying a voltage to a backgate formed in the substrate spaced from the doped region such that the barrier height between the traps and the backgate is reduced.

24. The method of claim 21, wherein said step of decreasing the resistance of the current path comprises the step of applying a voltage to the backgate such that the barrier width between the traps and the backgate is reduced wherein electrons are removed.

25. The method of claim 21, wherein said step of generating a current flow comprises the steps of creating a voltage difference between the source and the drain of a field effect transistor and applying a voltage to the gate of the field effect transistor to control the conductivity of the channel area.

22. A method for providing a variable resistance element in a semiconductor substrate, comprising the steps of:

generating a current flow through a doped region of a first conductivity type having an interface with a substrate of a second conductivity type;

increasing the resistance of the doped region by filling the traps with electrons; and

decreasing the resistance of the current path by removing electrons from the traps.

26. A method for forming a programmable resistor at a face of a layer of semiconductor of a first conductivity type, comprising the steps of:

forming a horizontal portion of a backgate of a second conductivity type by an implant into the face of the layer of semiconductor;

forming a vertical portion of the backgate continuous with the horizontal portion by an implant into the face of the layer of semiconductor; and

forming source and drain regions of the second conductivity type spaced by a channel area of the second conductivity type.

27. The method of claim 26 and further comprising the step of implanting an isolation region laterally enclosing the source drain, the backgate and the channel area.

28. The method of claim 26 and further comprising the step of forming a layer of thick insulator overlying the isolation region.

29. A method for forming a programmable resistor at a face of a layer of semiconductor of a first conductivity type, comprising the steps of:

forming a horizontal portion of a backgate of a second conductivity type by epitaxial growth;

forming a second layer of semiconductor of the first conductivity type adjacent the horizontal portion of the backgate;

forming a vertical portion of the backgate continuous with the horizontal portion by at least one implant into the face of the second layer of semiconductor; and

forming source and drain regions of the second conductivity type spaced by a channel area of the second conductivity type, the source, drain and channel area formed by at least one implant into the face of the second layer of semiconductor.

30. A method for forming a programmable resistor at a face of a layer of semiconductor of a first conductivity type, comprising the steps of:

forming a horizontal portion of a backgate of a second conductivity type by epitaxial growth;

forming a second layer of semiconductor of the first conductivity type adjacent the horizontal portion of the backgate;

forming a vertical portion of the backgate continuous with the horizontal portion of the backgate by implantation and a channel area of the second conductivity type by epitaxial growth of semiconductor of the second conductivity type;

forming a top layer of semiconductor of the second conductivity type vertically adjacent the channel area by epitaxial growth; and

defining the boundaries of a source region, a drain region and a vertical extension of the backgate, each vertically spaced from the channel area, by an etch of the top layer of semiconductor.

31. The method of claim 30 and further comprising the steps of:

performing at least one compensating implant into the face of the top layer of semiconductor to form an isolation region of the first conductivity type, the isolation region enclosing the channel area and the horizontal portion of the backgate; and

selectively creating isolation regions between the channel area, the vertical portion of the backgate by selectively damaging the lattice of the semiconductor therebetween by implantation.