Semiconductor memory cell and method of manufacturing the same

• US 5,065,215 A
• Filed: 06/22/1990
• Issued: 11/12/1991
• Est. Priority Date: 06/28/1989
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Kubota, Taishi
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Meier, Stephen D.
• Application Number:
  US07/542,427
• Time in Patent Office: 508 Days
• Field of Search: 357/23.6, 357/45, 357/41, 365/182
• US Class Current: 257/208
• CPC Class Codes: H10B 12/377 having a storage electrode extension located over the transistor

Abstract

A semiconductor memory includes a plurality of semiconductor memory cells formed in a matrix form on a semiconductor substrate, each semiconductor memory cell having a memory cell including a trench capacitor, a bit line, and a word line extending perpendicularly to the bit line. The word lines of semiconductor memory cells adjacent in a direction of the bit lines substantially vertically overlap each other. A method of manufacturing the above semiconductor memory includes the steps of forming a first word line of a given semiconductor memory cell, and forming a second word line of a semiconductor memory cell adjacent to the given semiconductor memory cell in a direction of the bit line on the first word line, so that the second word line overlaps the first word line in a substantially insulated state.

Claims

1. A semiconductor memory comprising:

a semiconductor substrate;

a plurality of semiconductor memory cells formed in a matrix form on said semiconductor substrate;

each semiconductor memory cells including a trench capacitor, a bit line, and a word line extending perpendicularly to said bit line,

said trench capacitor including a charge storage insulating layer in a trench formed on said semiconductor substrate, a counter electrode formed on said insulating layer, a first active region formed at an open portion of said trench, and a second active region which is separate from said first active region formed on said semiconductor substrate,

said word line being provided on said semiconductor substrate through an insulating layer which acts as a switching element in cooperation with said first and second active region,

said bit line being coupled to said second active region,

said switching element and said trench being arranged in a direction corresponding to the direction of said bit line, so that switching elements and trenches of neighboring cells are arranged reversely and in parallel t the bit line, and

word lines of the semiconductor memory cells which are adjacent in the direction of said bit lines being arranged to be separate from each other at a portion in which switching elements are neighbors and to substantially vertically overlap each other at a portion in which said trenches are neighbors.

2. A memory according to claim 1, said trench reaches said semiconductor substrate to increase a charge storage capacitance of said memory cells.

3. A memory according to claim 1, wherein said trench is formed between said overlapping word lines and another word line which is adjacent to said overlapping word lines.

4. A memory according to claim 1, wherein said memory cell includes a charge storage electrode inside said trench, said electrode being not insulated from said semiconductor substrate.