Non-volatile RAM with integrated compact static RAM load configuration

• US 5,065,362 A
• Filed: 06/02/1989
• Issued: 11/12/1991
• Est. Priority Date: 06/02/1989
• Status: Expired due to Term

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Kamp, David A., Herdt, Christian E., Dimmler, Klaus J., Weiner, Albert S.
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US07/361,033
• Time in Patent Office: 893 Days
• Field of Search: 365/154, 365/156, 365/184, 365/185, 365/226, 365/228
• US Class Current: 365/154
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor

Abstract

A non-volatile random access memory (NVRAM) cell of condensed size employs a pair of programmable threshold voltage devices, e.g. MNOS (metal nitride oxide semiconductor), SNOS (silicon nitride oxide semiconductor), SONOS (silicon oxide-nitride-oxide semiconductor) or floating gate transistors, in which different threshold voltage levels are established in accordance with the data signal levels existing on the data nodes of a flip flop, when the volatile data is stored in the programmable devices. During recall of the non-volatile stored data to the data nodes of the flip flop, the programmable devices actively conduct current to the data nodes to set the flip flop in the same state that existed when the data was stored. Power is supplied to the flip flop independently of the power supplied to the programmable devices. A single polysilicon conductor forms gates of transistors which connect the programmable devices to the data nodes and the gates of the flip flop transistors. A load device for each data node is integrated in the single polysilicon conductor. A dynamic program inhibit capability is achieved in each programmable device during the store operation, by applying a series of programming signal pulses.

Claims

1. A non-volatile static random access memory (NVSRAM) cell, comprising:

power supply means for supplying electrical power to said cell relative to a reference potential;

a flip flop having a true data node and a complement data node, the flip flop comprising a pair of cross-coupled flip flop transistors, one flip flop transistor having a control terminal connected to the true data node, a reference terminal electrically connected to the reference potential and an output terminal connected to the complement data node, and the other flip flop transistor having a control terminal connected to the complement data node, a reference terminal electrically connected to the reference potential and an output terminal connected to the true data node;

a pair of non-volatile circuits respectively connected to said true and complement data nodes, each non-volatile circuit comprising a programmable threshold voltage device having a gate terminal which is receptive of program and erase signals which establish different levels of threshold voltage for that programmable threshold voltage device in accordance with the level of the signal at its respective data node, a first transistor switch means having a control terminal which is receptive of a signal to allow the first transistor switch means to conduct and connect a corresponding programmable threshold voltage device to its respective data node when the program and erase signals are applied and when a data recall operation occurs, and a second switch means having a control terminal which is receptive of a signal to allow the second switch means to selectively conduct current from the power supply means through a corresponding programmable threshold voltage device and first transistor switch means to its respective data node during the data recall operation to establish a signal level at its respective data node related to the threshold voltage of the corresponding programmable threshold voltage device;

means commonly connecting the gate terminals of the programmable threshold voltage devices for conducting the program and erase signals to the gate terminals of the programmable threshold voltage devices; and

conductor means connected to the power supply means and including an integral resistive load for conducting power to the true data node and also including another integral resistive load for conducting power to the complement data node, the conductor means and the integral resistive loads energizing the flip flop to maintain the signals at the data nodes resulting from the previous operation of the flip flop as a static random access memory during application of the erase signals to the programmable threshold voltage devices.

2. A NVSRAM cell as defined in claim 1 wherein:

the conductor means further commonly connects the control terminals of the first transistor switch means of both non-volatile circuits; and

both first transistor switch means become conductive in response to the application of electrical power conducted by the conductor means from the power supply means.

3. A NVSRAM cell as defined in claim 1 or 2 wherein:

the conductor means includes a polysilicon conductor and each resistive load includes a segment of polysilicon having greater resistivity than the polysilicon in a remaining portion of the polysilicon conductor, each segment of greater resistivity polysilicon being located in the polysilicon conductor which leads to a corresponding data node.

4. A NVSRAM cell as defined in claim 3 wherein:

each segment of greater resistivity polysilicon is directly connected between the corresponding data node and the power supply means.

5. A NVSRAM cell as defined in claim 4 wherein:

the conductor means is a polysilicon conductor;

each of the resistive loads is a segment of polysilicon having greater resistivity than the polysilicon in the remaining portion of the polysilicon conductor and is located in the polysilicon conductor which leads to a corresponding data node;

the control terminal of each first transistor switch means and the control terminals of the flip flop transistors are each a portion of the polysilicon conductor; and

the polysilicon conductor is formed as a single layer.

6. A NVSRAM cell as defined in claim 1 wherein:

the power supply means comprises a first power supply means and a second power supply means;

the first power supply means supplies electrical power to the flip flop through the conductor means and both integral resistive loads;

the second power supply means supplies electrical power to each non-volatile circuit; and

each second switch means selectively connects the second power supply means to its corresponding programmable threshold voltage device.

7. A NVSRAM cell as defined in claim 6 wherein:

the conductor means further commonly connects the control terminals of the first transistor switch means of both non-volatile circuits; and

both first transistor switch means become conductive in response to the application of electrical power conducted by the conductor means from the power supply means.

8. A NVSRAM cell as defined in claim 7 wherein:

the conductor means includes a polysilicon conductor and each resistive load includes a segment of polysilicon having greater resistivity than the polysilicon in a remaining portion of the polysilicon conductor, each segment of greater resistivity polysilicon being located in the polysilicon conductor which leads to a corresponding data node.

9. A NVSRAM cell as defined in claim 8 wherein:

each segment of greater resistivity polysilicon is directly connected between the corresponding data node and the first power supply means.

10. A NVSRAM cell as defined in claim 9 wherein:

the conductor means is a polysilicon conductor;

each of the resistive loads is a segment of polysilicon having greater resistivity than the polysilicon in the remaining portion of the polysilicon conductor and is located in the polysilicon conductor which leads to a corresponding data node;

the control terminal of each first transistor switch means and the control terminals of the flip flop transistors are each a portion of the polysilicon conductor; and

the polysilicon conductor is formed as a single layer.

11. A NVSRAM cell as defined in claim 1, 2 or 6 wherein:

signal levels at the data nodes are stored in the non-volatile circuits to which the data nodes are connected during a store operation by establishing a programmable current conductivity characteristic for each programmable threshold voltage device of the non-volatile circuits in accordance with the signal level at a data node to which an associated programmable threshold voltage device is connected by a corresponding first transistor switch means;

the store operation includes a first erase step in which substantially equal conductivity characteristics of both programmable threshold voltage devices are established and an immediately following program step in which the conductivity of one of the programmable threshold voltage devices is changed; and

the conductor means and the integral resistive loads continually energize the flip flop throughout the store operation to maintain the signal levels at the data nodes throughout the store operation.

12. A NVSRAM cell as defined in claim 11 wherein:

signals are applied to the control terminals of each first transistor switch means continually throughout the store operation to maintain the conductivity of each first transistor switch means throughout the store operation.

13. A NVSRAM cell as defined in claim 12 wherein:

during the program step of the store operation a repeating pulse voltage signal is applied to the gate terminals of both programmable threshold voltage devices.

14. A NVSRAM cell as defined in claim 13 wherein:

each programmable threshold voltage device is fabricated from materials which include silicon nitride.

15. A NVSRAM cell as defined in claim 12 wherein:

during the erase step of the store operation a signal of a negative potential relative to the potentials of the signals at both data nodes is applied to the gate terminals of both programmable threshold voltage devices.

16. A NVSRAM cell as defined in claim 15 wherein:

during the program step of the store operation a repeating pulse voltage signal is simultaneously applied to the gate terminals of both programmable threshold voltage devices.

17. A NVSRAM cell as defined in claim 15 wherein:

the erase signal applied to the gate terminals of the programmable threshold voltage devices during the erase step establishes a common threshold voltage on both programmable threshold voltage devices;

a program signal applied to the gate terminals of the programmable threshold voltage devices during the program step establishes a different conductivity characteristic of a corresponding programmable threshold voltage device in accordance with the data level signal on one data node while leaving the conductivity characteristic of the other programmable threshold voltage device substantially unchanged from the level established by the erase signal; and

the erase signal and the program signal are respectively different voltage polarities.

18. A NVSRAM cell as defined in claim 17 wherein:

the program signal is a repeating pulse signal which is applied to the gate control terminals of the programmable threshold voltage devices and which has a potential continually of the opposite polarity relative to the erase signal.

19. A NVSRAM cell as defined in claim 18 wherein:

each programmable threshold voltage device is a silicon nitride oxide semiconductor (SNOS) transistor.