Video RAM double buffer select control

• US 5,065,368 A
• Filed: 05/16/1989
• Issued: 11/12/1991
• Est. Priority Date: 05/16/1989
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Tamlyn, Robert, Williams, Todd, Tomashot, Steven W., Gupta, Satish, Henderson, Randall L., Hiltebeitel, Nathan R.
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US07/352,442
• Time in Patent Office: 910 Days
• Field of Search: 365/189.05, 365/230.05, 365/230.09, 365/233, 365/239, 365/240
• US Class Current: 365/230.05
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413

Abstract

An implementation of a serial access memory register that facilitates the selecting from two alternate frame buffers on a per pixel basis. The frame buffers are each stored in a portion of a row in a single video RAM. Following data transfer to the serial access memory register, data from each of the two frame buffers is available. A double buffer select signal controls the selection of which half of the serial access memory register will put data on the output bus for each serial clock signal. The serial clock increments the address pointers in both halves of the serial access memory port simultaneously.

Claims

1. A dual-port memory comprising:

a memory array having a plurality of memory elements each of which is accesses at random by a row and column address input to enable writing in or reading out of data at said row and column location;

first and second serial access memory means, each selectively accessing a specified portion of the data of a row of said memory elements in parallel;

control means for serially transferring data between said first and second serial access memory means and an output port in synchronism with a clock signal; and

selection means for selectively actuating said control means to couple said first or secod serial access memory means to said output port, said selection means being responsive to a selection control signal which may be varied arbitrarily between successive cycles of said clock signal to select a particular one of said serial access memory means.

2. The dual-port memory of claim 1 wherein said selection means comprises a serial access address means for generating an address in either said first or second serial access memory means, and wherein said selection control signal determines which serial access memory means said address will access.

3. The dual-port memory of claim 2, wherein said serial access address means comprises two serial address counters each generating interleaved serial access memory addresses and wherein said selection control signal modifies each of said two addresses to access said first or second serial access memory means.

4. The dual-port memory of claim 1 wherein said selection means comprises a multiplxer responsive to said selection control signal.

5. In a semiconductor memory array having elements arranged in rows and columns, wherein said columns are grouped into first and second frame buffers, and wherein said first and second frame buffers each represent a plurality of picture elements on a display device, a method for serially accessing said semiconductor memory to present an element from either said first or said second frame buffer comprising the steps of:

decoding a row address to select a row of memory elements;

loading a portion of said row representing a first frame buffer into a first serial access memory register;

loading a portion of said row representing a second frame buffer into a second serial access memory register;

applying a clock signal to said first and second serial access memory registers to access an element in each register corresponding to a given display device picture element; and

applying selection signal to select which of said elements to output through an output port, said selection signal being arbitrarily variable between successive cycles of said clock signal to select a particular one of said registers.

6. In a semiconductor memory array having elements arranged in rows and columns, wherein said columns are grouped into first and second frame buffers, and wherein said first and second frame buffers each represent a plurality of picture elements on a display device, a method for serially accessing said semiconductor memory to present an element from either said first or said second frame buffer comprising the steps of:

decoding a row address to select a row of memory elements;

loading a portion of said row representing a first frame buffer into a first serial access memory register;

loading a portion of said row representing a second frame buffer into a second serial access memory register;

generating a serial access address in response to a clock signal;

modifying said serial access address by applying a selection signal to select said first or second serial access memory register, said selection signal being arbitrarily variable bewteen successive cycles of said clock signal to select a particular one of said registers; and

accessing a picture element at said modified address and transferring said element to an output port.

7. In a dual-port memory comprising a random access memory array having a plurality of rows and columns and respective locations corresponding to the intersections of said rows and columns, means for coupling the location corresponding to a row address input and a column address input to a first port, a plurality of serial access memory registers, each of which has columns corresponding to columns of said array, and means for transferring data in parallel between a selected row of said memory array and said registers, a method of controlling the serial transfer of data between said registers and a second port, said method including the steps of storing a count corresponding to a colyumn of a selected one of said registers, indexing said count in synchronism with a clock signal to address successive columns of the selected register, generating a selection control signal independently of said count for selecting one of said registers, and coupling said second port to the column corresponding to said count of the register selected by said control signal, whereby different registers may be accessed on successive counts in accordance with said control signal.

8. A dual-port memory comprising a random access memory array having a plurality of rows and columns and respective locations corresponding to the intersections of said rows and columns, means for coupling the location corresponding to a row address input and a column address input to a first port, a plurality of serial access memory registers, each of which has columns corresponding to columns of said array, means for transferring data in parallel between a selected row of said memory array and said registers, and means for controlling the serial transfer of data between said registers and a second port, said controlling means including means for storing a count corresponding to a column of a selected one of said registers, means for indexing said count in synchronism with a clock signal to address successive columns of the selected register, means for generating a selection control signal independently of said count for selecting one of said registers, and means for coupling said second port to the column corresponding to said count of the register selected by said control signal, whereby different registers may be accessed on successive counts in accordance with said control signal.