Fractional-division synthesizer for a voice/data communications systems

• US 5,065,408 A
• Filed: 04/26/1990
• Issued: 11/12/1991
• Est. Priority Date: 04/26/1990
• Status: Expired due to Term

• Current Assignee: Quarterhill Inc. (f/k/a Wi-LAN Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Gillig, Steven F.
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US07/515,000
• Time in Patent Office: 565 Days
• Field of Search: 375/8, 375/9, 375/62, 375/65, 375/97, 375/7, 328/14, 364/721, 364/851, 455/76, 455/183, 455/259, 455/260, 455/86, 455/87, 331/1 R, 331/1 A, 331/17, 331/179, 332/100, 332/101, 332/103
• US Class Current: 375/222
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider

Abstract

A fractional-division synthesizer for a digital transceiver is disclosed in which the fractional divisor may be separated into an integer, N, and a fraction made up of two integers, [n/d]. The integer n is the numerator of the fraction part of the fractional divisor. The integer N is the whole number portion of the fractional divisor. The integer d multiplied by the value of the transceiver channel spacing is algebraically related to the frequency of the reference oscillator. A bit rate clock is also derived from the reference oscillator.

Claims

1. A fractional-division synthesizer for a digital radio transceiver, the synthesizer providing an output signal having a non-integer frequency relationship to a reference signal frequency, the fractional-division synthesizer comprising:

a phase comparator having at least a first input and at least a first output;

a programmable frequency divider with a non-integer divisor having a value of the sum of an integer,N, and a fraction determined by the ratio of integer, {n/d}, said programmable frequency divider having at least a first input and at least a first output, said first output of said programmable frequency divider coupled to said first input of said frequency comparator, said programmable frequency divider dividing the frequency of said output signal;

means for generating an output signal having a first frequency when said non-integer divisor has a first value determined by a first integer value of n and for generating an output signal having a second frequency when said non-integer divisor has a second value determined by the next larger integer value of n, an input of said means for generating coupled to said first output of said phase comparator, an output of said means for generating an output signal coupled to said first input of said programmable frequency divider;

means for generating a first reference signal;

means, responsive to said means for generating a first reference signal, for producing a second reference signal coupled to a second input of said phase comparator, said second reference signal having a frequency integerly related to the product of d times the difference of said first output signal frequency and said second output signal frequency; and

means, responsive to said means for generating a first reference signal, for producing a third reference signal coupled to a digital portion of said digital transceiver, said third reference signal having a frequency algebraically related to said first reference signal frequency.

2. A fractional-division synthesizer in accordance with claim 1 wherein said means for producing said second reference signal further comprises a frequency divider coupled to said phase comparator and having an integer divisor value.

3. A fractional-division synthesizer in accordance with claim 1 wherein said third reference signal frequency is algebraically related to said second reference signal frequency by an integer value.

4. A method of frequency synthesis for a digital radio transceiver employing a fractional-division synthesizer, the synthesizer providing at least one output signal with a frequency having a non-integer frequency relationship to a reference signal frequency, comprising the steps of:

programmably frequency dividing the output signal of the synthesizer with a non-integer divisor having a value of the sum of an integer,N, and a fraction determined by the ratio of integers {n/d};

generating an output signal having a first frequency when said non-integer divisor has a first value determined by a first integer value of n and generating an output signal having a second frequency when said non-integer divisor has a second value determined by the next larger integer value of n;

generating a first reference signal;

producing, in response to said generating a first reference signal step, a second reference signal, said second reference signal having a frequency integrally related to the product of d times the difference in frequency of said first and second output signals, and utilized in said step of generating said output signal; and

producing, in response to said generating a first reference signal step, a third reference signal coupled to a digital portion of said digital transceiver, said third reference signal frequency being algebraically related to the frequency of said first reference signal.

5. A digital radio transceiver employing a fractional-division synthesizer, the synthesizer providing a synthesizer output signal having a non-integer frequency relationship to a reference signal frequency, the digital radio transceiver comprising:

a digital transmitter employing a digital modulator responsive to a clock signal;

a phase comparator having at least a first input and a first output;

a programmable frequency divider with a non-integer divisor having a value of the sum of an integer,N, and a fraction determined by the ratio of integers {n/d}, said programmable frequency divider having at least a first input and at least a first output, said first output of said programmable frequency divider coupled to said first input of said phase comparator;

means for generating a synthersizer output signal having a first frequency when said non-integer divisor has a first value determined by a first integer value of n and for generating a synthesizer output signal having a second frequency when said non-integer divisor has a second value determined by the next larger integer value of n, an output of said means for generating coupled to a first input of said programmable frequency divider;

means for generating a first reference signal;

means, responsive to said means for generating a first reference signal, for producing a second reference signal coupled to a second input of said phase comparator, said second reference signal having a frequency integrally related to the product of d times the difference of said first output signal frequency and said second output signal frequency; and

means, responsive to said means for generating a first reference frequency, for producing said clock signal coupled to said digital modulator, said clock signal having a frequency algebraically related to said first reference signal frequency.

6. A digital radio transceiver in accordance with claim 5 wherein said means for producing said second reference signal further comprises a frequency divider coupled to said phase comparator and having an integer divisor value.

7. A digital radio transceiver in accordance with claim 5 wherein said clock signal frequency is algebraically related to said second reference signal frequency by an integer value.