Method and apparatus for mapping a digital signal carrier to another

• US 5,067,126 A
• Filed: 08/04/1989
• Issued: 11/19/1991
• Est. Priority Date: 05/30/1989
• Status: Expired due to Fees

• Current Assignee: Telecommunications Research Laboratories
• Original Assignee: Telecommunications Research Laboratories
• Inventors: Moore, Thomas E.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Chin, Wellington
• Application Number:
  US07/389,768
• Time in Patent Office: 837 Days
• Field of Search: 370/84, 370/112, 370/1, 370/102, 370/60, 370/60.1, 370/94.1, 370/94.2, 370/94.3, 370/58.1, 370/58.2, 370/58.3, 370/100.1, 375/112
• US Class Current: 370/544
• CPC Class Codes: H04J 3/076 Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking
• CPC Class Codes: Y10S 370/907 Synchronous optical network, SONET

Abstract

A DS-3 to 28 VT1.5 SONET Interface Circuit is shown, without using standard intermediate DS-2 and DS-1 Desynchronizer Phase-Lock Loops. The elimination of DS-2 and DS-1 Desynchronizer Phase Lock Loops results in a significant reduction in cost and complexity of SONET interface circuits for the existing asynchronous digital multiplex hierarchy.

Claims

1. A process for the mapping of a first digital signal carrier carrying a first multiplexed digital signal to a second digital signal carrier comprising:

demultiplexing the first digital signal to produce a second digital signal and to derive a gapped clock;

writing the second digital signal to an elastic store using the gapped clock; and

reading the second digital signal from the elastic store.

2. The process of claim 1 in which the second digital signal is a SONET signal.

3. Apparatus for the mapping of a first digital signal carrier carrying a first digital signal to a second digital signal carrier comprising:

a demultiplexer for demultiplexing the first digital signal to produce a second digital signal;

gapping means for gapping the first digital signal carrier to derive a gapped clock;

writing means for writing the second digital signal to an elastic store using the gapped clock; and

reading means for reading the second digital signal from the elastic store.

4. Apparatus for mapping a DS-3 digital signal to a SONET signal, the apparatus comprising:

a first demultiplexer for demultiplexing the DS-3 signal to generate a DS-2 signal and to generate a gapped DS-2 clock;

a second demultiplexer to demultiplex the DS-2 signal to generate a DS-1 signal and to generate a gapped DS-1 clock; and

bit stuffing means for bit stuffing the DS-1 signal to create a SONET signal.