Wireless alarm system

• US 5,067,136 A
• Filed: 07/12/1990
• Issued: 11/19/1991
• Est. Priority Date: 11/02/1988
• Status: Expired due to Term

• Current Assignee: M&FC Holding, LLC, NorthPeak Wireless, LLC
• Original Assignee: Axonn LLC (Globalstar Incorporated)
• Inventors: Davis, Robert J., Rouquette, Robert E., Sanderford, H. Britton Jr., Arthur, James D.
• Primary Examiner(s): Tarcza, Thomas H.
• Assistant Examiner(s): CAIN, DAVID C
• Application Number:
  US07/551,815
• Time in Patent Office: 495 Days
• Field of Search: 375/1, 380/34
• US Class Current: 375/142
• CPC Class Codes: G08B 25/10 using wireless transmission systems G08B25/009 takes precedence
• CPC Class Codes: H04B 1/7075 with code phase acquisition
• CPC Class Codes: H04B 1/70756 Jumping within the code, i.e. masking or slewing H04B1/70758 takes precedence
• CPC Class Codes: H04B 1/7077 Multi-step acquisition, e.g. multi-dwell, coarse-fine or validation
• CPC Class Codes: H04B 2201/70715 with application-specific features

Abstract

A wireless alarm system using spread spectrum transmitters, fast frequency shift keying, spread spectrum receivers and computer with a display. The spread spectrum transmitter includes an oscillator coupled to a microprocessor with chip code generation means, preamble register, address register and data register. The spread spectrum receiver acquires synchronization of the spread spectrum signal using a microprocessor coupled to the quieting, signal strength or baseband output of the receiver, with a two step algorithm. The steps comprise achieving a coarse lock and a fine lock to the spread spectrum signal.

Claims

1. In a method for communicating over a communications channel using spread spectrum modulation from a transmitter to a receiver by modulating a data-bit sequence with a chip sequence having a pseudorandom chip code, the improvement characterized by:

generating a preamble for receiver chip code synchronization having one of the group of alternating 1-bits and 0-bits, wherein the data-bit sequence ranges from a one to one ratio to a ten to one ratio.

2. In an apparatus for communicating over a communications channel using spread spectrum modulation from a transmitter to a receiver comprising means for modulating a data-bit sequence with a chip sequence having a pseudorandom chip code, the improvement characterized by:

means for generating a preamble for chip code synchronization having one of the group of alternating 1-bits and 0-bits, wherein the data-bid sequence ranges from a one to one ratio to a ten to one ratio.

3. A hybrid data/spread spectrum transmission system for transmitting information data bits having "1" data bits and "0" data bits over a communications channel, comprising:

at least one transmitter including

means for generating synchronization-data bits;

means using amplitude shift keying having at least a first voltage level for representing the "1" data bits and a second voltage level for representing the "0" data bits, for modulating a carrier signal with the synchronization-data bits and information-data bits;

means using binary-phase-shift keying for modulating the carrier signal with a spread spectrum chip code;

means for transmitting the carrier signal having the amplitude shift keying and binary-phase-shift keying modulation over said communications channel;

at least one receiver including

means responsive to the binary-phase-shift keying for demodulating the spread spectrum embedded in the carrier signal from said communications channel; and

means responsive to the amplitude shift keying with the synchronization-data bits for detecting the first voltage level and the second voltage level of the carrier signal and for determining, based on a plurality of detected synchronization-data bits, a voltage threshold between the detected first voltage level and the detected second voltage level, for detecting subsequent information data bits.

4. The hybrid data/spread spectrum transmission system as set forth in claim 3, further comprising:

means for generating a preamble for chip code synchronization having one of the group of alternating 1-bits and 0-bits, wherein the data-bit sequence ranges from a one to one ratio to a ten to one ratio.

5. The hybrid data/spread spectrum transmission system as set forth in claim 3, wherein said detecting means includes detecting the first voltage level and the second voltage level of the carrier signal and for determining, based on a plurality of detected subsequent information-data bits, an adaptive voltage threshold between the detected first voltage level and the detected second voltage level, for detecting information data bits.

6. A hybrid data/spread spectrum transmission system for transmitting information data bits having "1" data bits and "0" data bits, comprising:

at least one transmitter including

means for generating synchronization-data bits;

means using amplitude shift keying having at least a first voltage level for representing the "1" data bits and a second voltage level for representing the "0" data bits, for modulating a carrier signal with the synchronization-data bits and information-data bits;

means using frequency-shift keying for modulating the carrier signal with a spread spectrum chip code;

means for transmitting the carrier signal having the amplitude shift keying and frequency-shift keying modulation;

at least one receiver including

means responsive to the frequency-shift keying for demodulating the spread spectrum embedded in the carrier signal; and

means responsive to the amplitude shift keying with the synchronization-data bits for detecting the first voltage level and the second voltage level of the carrier signal and for determining, based on a plurality of detected synchronization-data bits, voltage threshold between a detected first voltage level and a detected second voltage level, for detecting subsequent information data bits.

7. The hybrid data/spread spectrum transmission system as set forth in claim 6, further comprising:

means for generating a preamble for chip code synchronization having one of the group of alternating 1-bits and 0-bits, wherein the data-bid sequence ranges from a one to one ratio to a ten to one ratio.

8. The hybrid data/spread spectrum transmission system as set forth in claim 6, wherein said detecting means includes detecting the first voltage level and the second voltage level of the carrier signal and for determining, based on a plurality of detected information-data bits, an adaptive voltage threshold between the detected first voltage level and the detected second voltage level, for detecting information data bits.

9. An apparatus for rejecting impulse noise from a received signal modulated with a spread spectrum chip code, comprising:

means for correlating the received signal with a the spread spectrum chip code to generate the correlation signal;

means for searching the correlation signal for the highest correlation signal peak and measuring said highest correlation signal peak as a first correlation voltage level;

means for measuring signal strength with at least one chip delay from the highest correlation signal peak as a second correlation voltage level; and

means responsive to the second correlation voltage level being approximately equal to the first correlation voltage level for rejecting the correlation signal as noise.

10. An apparatus for rejecting impulse noise from a received signal modulated with a spread spectrum chip code, comprising:

means for correlating the received signal with a the spread spectrum chip code to generate the correlation signal;

means for searching the correlation signal for the highest correlation signal peak and measuring said highest correlation signal peak as a first correlation voltage level;

means for measuring signal strength with at least one chip delay from the highest correlation signal peak as a second correlation voltage level; and

means responsive to the second correlation voltage level being much less than the first correlation voltage level for rejecting the correlation signal as noise.

11. A method using a processor for rejecting impulse noise from a received signal modulated with a spread spectrum chip code, comprising the steps, using said processor, of:

correlating the received signal with a the spread spectrum chip code to generate a correlation signal;

searching the correlation signal for the highest correlation signal peak;

measuring said highest correlation signal peak as a first correlation voltage level;

measuring signal strength with at least one chip delay from said highest correlation signal peak as a second correlation voltage level; and

rejecting, in response to the second correlation voltage level being approximately equal to the first correlation voltage level, the correlation signal.

12. The method as set forth in claim 11, further including the step of:

outputting in response to the second correlation voltage signal being much less than the first correlation voltage level, the correlation signal.

13. An apparatus for achieving spread spectrum chip code synchronization, coupled to a receiver having an output, comprising:

means coupled to said receiver output for measuring signal strength of a received signal having spread spectrum;

means coupled to said measuring means, responsive to when the signal strength is above a noise floor for searching through a chip code for coarsely aligning within 1/2 chip the received signal with the chip code, and responsive to when the signal strength is below the noise floor for detecting a maximum correlation value without searching the entire chip code sequence; and

means coupled to said aligning means for aligning the chip code with the received signal.

14. A method using a processor for achieving spread spectrum chip code synchronization coupled to a receiver having an output, comprising the steps, using said processor, of:

measuring signal strength of a received signal having spread spectrum;

searching, in response to when the signal strength is above a noise floor, through the entire chip code sequence for coarsely aligning within 1/2 chip the received signal with the chip code;

detecting, in response to when the signal strength is below the noise floor, a maximum correlation value without searching the entire chip code sequence in response to the received signal; and

aligning the chip code with the received signal.