Method for anodizing a polysilicon layer lower capacitor plate of a DRAM to increase capacitance

• US 5,068,199 A
• Filed: 05/06/1991
• Issued: 11/26/1991
• Est. Priority Date: 05/06/1991
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sandhu, Gurtej S.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Thomas, Tom
• Application Number:
  US07/696,438
• Time in Patent Office: 204 Days
• Field of Search: 437/38, 437/47, 437/48, 437/52, 437/60, 437/191, 437/193, 437/195, 437/228, 437/233, 437/235, 437/919, 357/23.6, 357/51, 204/129.1, 156/628, 156/627
• US Class Current: 438/255
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 21/321 After treatment
• CPC Class Codes: H01L 28/84 being a rough surface, e.g. using hemispherical grains
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: Y10S 438/96 Porous semiconductor

Abstract

A method for fabricating a DRAM cell having enhanced-capacitance attributable to the use of a porous structured polycrystalline silicon layer storage node capacitor plate. The present invention is particularly applicable to DRAM cells which employ a stacked capacitor design. Such designs generally employ a conductively-doped polycrystalline silicon layer as the storage node, or lower, capacitor plate. A microstructure is formed by anodizing the storage node plate layer in a solution of hydrofluoric acid to produce microstructures resembling elongated pores in the storage node plate layer. This is followed by the deposition of a thin conformal (typically less than 100 Angstroms) silicon nitride layer which in turn is followed by the deposition of a second polycrystalline silicon (poly) layer, which functions as the capacitor field plate. Since the nitride layer is thin in comparison to the elongated pores in the storage node plate layer, capacitive area is substantially augmented. Cell capacitance can be increased by more than 1,000 percent using a storage node plate having microstructures thus formed.

Claims

1. A method of fabricating a storage capacitor having an intrinsic silicon layer doped with an impurity to produce an extrinsic first doped silicon conductive layer forming a storage node capacitor plate comprising the following steps:

a) anodizing said first doped silicon layer, said anodizing producing a porous upper surface by consuming portions of said first doped silicon layer to produce micro structures resembling elongated pores, a porosity of said porous upper surface measured by a porous film density, said porous film density equal to the percent of weight loss for a given volume of said first doped silicon layer experience during said anodizing, said anodizing increasing a surface area of said storage node capacitor plate;

b) depositing a dielectric layer to overlie said first doped silicon layer, said dielectric layer having lower and upper surfaces, the porous upper surface of said first doped silicon layer being in contact at all points with the lower surface of said dielectric layer, said dielectric layer being substantially conformal with the porous upper surface of said first doped silicon layer; and

c) depositing of an intrinsic silicon layer doped with an impurity to produce an extrinsic second doped silicon conductive layer to overlie said dielectric layer, said second doped silicon layer having lower and upper surfaces, said lower surface being in contact with the upper surface of said dielectric layer and being substantially conformal thereto.

2. The method of claim 1, wherein said first and second doped silicon layers comprise polycrystalline silicon.

3. The method of claim 1, wherein said first and second doped silicon layers comprise monocrystalline silicon.

4. The method of claim 1, wherein said first and second doped silicon layers are positively doped.

5. The method of claim 4, wherein said impurity is a trivalent atom comprising aluminum, boron and gallium, said trivalent atom effecting said positively doped layers.

6. The method of claim 1, wherein said first and second doped silicon layers are negatively doped layers.

7. The method of claim 6, wherein said impurity is a pentavalent atom comprising arsenic, antimony, and phosphorus, said pentavalent atom effecting said negatively doped layers.

8. The method of claim 1, wherein said first and second doped silicon layers are oppositely doped, one of said doped layers being negatively doped and one of said doped layers being positively doped.

9. The method of claim 8, wherein said impurity is a trivalent atom comprising aluminum, boron and gallium, said trivalent atom effecting said positively doped layers.

10. The method of claim 8, wherein said impurity is a pentavalent atom comprising arsenic, antimony, and phosphorus, said pentavalent atom effecting said negatively doped layers.

11. The method of claim 1, wherein said depositing of the dielectric layer further comprises depositing a silicon nitride layer.

12. The method of claim 11 wherein the thickness of said silicon nitride layer is less than 100 Angstroms.

13. The method of claim 1, wherein said anodizing further comprises submerging said first doped silicon layer in a container of electrolytic solution comprising hydrofluoric acid and subjecting said first doped silicon layer and said electrolytic solution to an electrolytic current, said current generated between two electrodes, one being an anode and one being a cathode.

14. The method of claim 13, wherein said anode further comprises said first doped silicon layer.

15. The method of claim 13, wherein said first doped silicon layer is a portion of a semiconductor wafer, said anode comprising said wafer.

16. The method of claim 13, wherein said container is defined by walls, said cathode comprising said walls.

17. The method of claim 13, wherein said cathode further comprises a platinum electrode immersed in said electrolytic solution parallel to said first doped silicon layer.

18. The method of claim 13, further comprising applying said electrolytic current within the range of 10 mA/cm² and 100 mA/cm² in said hydrofluoric acid solution having a concentration between 10 to 60 percent by weight.

19. The method of claim 18, further comprising regulating said porous film density within the range of 20 to 70 percent, with a preferred porous film density of about 45 percent.

20. The method of claim 13, further comprising the step of a first texturizing of the upper surface of said first doped silicon layer prior to said anodizing to produce three-dimensional asperities to increase current flow and initiate pores in said first doped silicon layer during said anodizing.

21. The method of claim 20, wherein said first texturizing comprises:

a) growing a layer of oxide on said first doped silicon layer prior to said anodizing to produce inhomogeneities to increase current flow and initiate pores in said first doped silicon layer during said anodizing; and

b) removing of said layer of oxide to expose said first doped silicon layer.

22. The method of claim 21, wherein said growing of said layer of oxide is accomplished with a wet oxidation.

23. The method of claim 21, wherein said removing is accomplished with a wet oxide etch.

24. The method of claim 13, further comprising the step of a second texturizing of the porous upper surface subsequent to said anodizing to increase the surface area of said storage node capacitor plate.

25. The method of claim 24, wherein said second texturizing comprises:

a) growing a layer of oxide on the porous upper surface subsequent to said anodizing to increase porous film density; and

b) removing of said layer of oxide to expose said porous upper surface.

26. The method of claim 23, wherein said growing of said layer of oxide is accomplished with a wet oxidation.

27. The method of claim 23, wherein said removing is accomplished with a wet oxide etch.

28. A method of fabricating an enhanced-capacitance DRAM cell comprising the following steps:

a) constructing a field-effect transistor (FET) on a silicon substrate, a first portion of said substrate being conductively-doped to function as the FET'"'"'s access node junction and a second portion of said substrate being conductively-doped to function as the FET'"'"'s storage node junction;

b) fabricating a storage capacitor having an intrinsic silicon layer doped with an impurity to produce an extrinsic first doped silicon conductive layer forming a storage node capacitor plate in electrical communication with said storage node junction comprising the following steps;

1) anodizing said first doped silicon layer, said anodizing producing a porous upper surface by consuming portions of said first doped silicon layer to produce micro structures resembling elongated pores, a porosity of said porous upper surface measured by a porous film density, said porous film density equal to the percent of weight loss for a given volume of said first doped silicon layer experience during said anodizing, said anodizing increasing a surface area of said storage node capacitor plate;

2) depositing a dielectric layer to overlie said first doped silicon layer, said dielectric layer having lower and upper surfaces the porous upper surface of said first doped silicon layer being in contact at all points with the lower surface of said dielectric layer, said dielectric layer being substantially conformal with the porous upper surface of said first doped silicon layer; and

3) depositing of an intrinsic silicon layer doped with an impurity to produce an extrinsic second doped silicon conductive layer to overlie said dielectric layer, said second doped silicon layer having lower and upper surfaces, said lower surface being in contact with the upper surface of said dielectric layer and being substantially conformal thereto.

29. The method of claim 28, further comprises:

a) forming an oxide layer to provide a texturized surface;

b) performing a wet oxidation to form said oxide layer; and

c) removing said oxide layer with a wet oxide etch.

30. The method of claim 28, wherein said first and second doped silicon layers comprise polycrystalline silicon and monocrystalline silicon.

31. The method of claim 28, further comprising said first and second doped silicone layers being positively doped, said first and second doped silicon layers being negatively doped, and said first and second doped silicon layers being oppositely doped, one of said doped layers being negatively doped and one of said doped layers being positively doped.

32. The method of claim 28, wherein said impurity is a trivalent atom comprising aluminum, boron and gallium.

33. The method of claim 28, wherein said impurity is a pentavalent atom comprising arsenic, antimony, and phosphorus.

34. The method of claim 28, wherein said depositing of the dielectric layer further comprises depositing a silicon nitride layer.

35. The method of claim 34, wherein the thickness of said silicon nitride layer is less than 100 Angstroms.

36. The method of claim 28, wherein said anodizing further comprises submerging said first doped silicon layer in a container of electrolytic solution comprising hydrofluoric acid and subjecting said first doped silicon layer and said electrolytic solution to an electrolytic current, said current generated between two electrodes, one being an anode and one being a cathode.

37. The method of claim 36, wherein said anode comprises said first doped silicon layer and said silicon substrate.

38. The method of claim 36, wherein said container is defined by walls, said cathode comprising said walls and a platinum electrode immersed in said electrolytic solution parallel to said first doped silicon layer.

39. The method of claim 36, further comprising applying said electrolytic current within the range of 10 mA/cm² and 100 mA/cm² in said hydrofluoric acid solution having a concentration between 10 to 60 percent by weight.

40. The method of claim 39, further comprising regulating said porous film density within the range of 20 to 70 percent, with a preferred porous film density of about 45 percent.

41. The method of claim 36, further comprising the step of texturizing of the upper surface of said first doped silicon layer prior to said anodizing to produce three-dimensional asperities to increase current flow and initiate pores in said first doped silicon layer during said anodizing.

42. The method of claim 41, wherein said texturizing comprises:

a) growing a layer of oxide on said first doped silicon layer prior to said anodizing to produce inhomogeneities to increase current flow and initiate pores in said first doped silicon layer during said anodizing; and

b) removing of said layer of oxide to expose said first doped silicon layer.

43. The method of claim 36, further comprising the step of texturizing of the porous upper surface subsequent to said anodizing to increase the surface area of said storage node capacitor plate.

44. The method of claim 43, wherein said texturizing comprises:

a) growing a layer of oxide on the porous upper surface subsequent to said anodizing to increase porous film density; and

b) removing of said layer of oxide to expose said porous upper surface.