Method for anodizing a polysilicon layer lower capacitor plate of a DRAM to increase capacitance
First Claim
1. A method of fabricating a storage capacitor having an intrinsic silicon layer doped with an impurity to produce an extrinsic first doped silicon conductive layer forming a storage node capacitor plate comprising the following steps:
- a) anodizing said first doped silicon layer, said anodizing producing a porous upper surface by consuming portions of said first doped silicon layer to produce micro structures resembling elongated pores, a porosity of said porous upper surface measured by a porous film density, said porous film density equal to the percent of weight loss for a given volume of said first doped silicon layer experience during said anodizing, said anodizing increasing a surface area of said storage node capacitor plate;
b) depositing a dielectric layer to overlie said first doped silicon layer, said dielectric layer having lower and upper surfaces, the porous upper surface of said first doped silicon layer being in contact at all points with the lower surface of said dielectric layer, said dielectric layer being substantially conformal with the porous upper surface of said first doped silicon layer; and
c) depositing of an intrinsic silicon layer doped with an impurity to produce an extrinsic second doped silicon conductive layer to overlie said dielectric layer, said second doped silicon layer having lower and upper surfaces, said lower surface being in contact with the upper surface of said dielectric layer and being substantially conformal thereto.
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Abstract
A method for fabricating a DRAM cell having enhanced-capacitance attributable to the use of a porous structured polycrystalline silicon layer storage node capacitor plate. The present invention is particularly applicable to DRAM cells which employ a stacked capacitor design. Such designs generally employ a conductively-doped polycrystalline silicon layer as the storage node, or lower, capacitor plate. A microstructure is formed by anodizing the storage node plate layer in a solution of hydrofluoric acid to produce microstructures resembling elongated pores in the storage node plate layer. This is followed by the deposition of a thin conformal (typically less than 100 Angstroms) silicon nitride layer which in turn is followed by the deposition of a second polycrystalline silicon (poly) layer, which functions as the capacitor field plate. Since the nitride layer is thin in comparison to the elongated pores in the storage node plate layer, capacitive area is substantially augmented. Cell capacitance can be increased by more than 1,000 percent using a storage node plate having microstructures thus formed.
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Citations
44 Claims
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1. A method of fabricating a storage capacitor having an intrinsic silicon layer doped with an impurity to produce an extrinsic first doped silicon conductive layer forming a storage node capacitor plate comprising the following steps:
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a) anodizing said first doped silicon layer, said anodizing producing a porous upper surface by consuming portions of said first doped silicon layer to produce micro structures resembling elongated pores, a porosity of said porous upper surface measured by a porous film density, said porous film density equal to the percent of weight loss for a given volume of said first doped silicon layer experience during said anodizing, said anodizing increasing a surface area of said storage node capacitor plate; b) depositing a dielectric layer to overlie said first doped silicon layer, said dielectric layer having lower and upper surfaces, the porous upper surface of said first doped silicon layer being in contact at all points with the lower surface of said dielectric layer, said dielectric layer being substantially conformal with the porous upper surface of said first doped silicon layer; and c) depositing of an intrinsic silicon layer doped with an impurity to produce an extrinsic second doped silicon conductive layer to overlie said dielectric layer, said second doped silicon layer having lower and upper surfaces, said lower surface being in contact with the upper surface of said dielectric layer and being substantially conformal thereto. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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28. A method of fabricating an enhanced-capacitance DRAM cell comprising the following steps:
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a) constructing a field-effect transistor (FET) on a silicon substrate, a first portion of said substrate being conductively-doped to function as the FET'"'"'s access node junction and a second portion of said substrate being conductively-doped to function as the FET'"'"'s storage node junction; b) fabricating a storage capacitor having an intrinsic silicon layer doped with an impurity to produce an extrinsic first doped silicon conductive layer forming a storage node capacitor plate in electrical communication with said storage node junction comprising the following steps; 1) anodizing said first doped silicon layer, said anodizing producing a porous upper surface by consuming portions of said first doped silicon layer to produce micro structures resembling elongated pores, a porosity of said porous upper surface measured by a porous film density, said porous film density equal to the percent of weight loss for a given volume of said first doped silicon layer experience during said anodizing, said anodizing increasing a surface area of said storage node capacitor plate; 2) depositing a dielectric layer to overlie said first doped silicon layer, said dielectric layer having lower and upper surfaces the porous upper surface of said first doped silicon layer being in contact at all points with the lower surface of said dielectric layer, said dielectric layer being substantially conformal with the porous upper surface of said first doped silicon layer; and 3) depositing of an intrinsic silicon layer doped with an impurity to produce an extrinsic second doped silicon conductive layer to overlie said dielectric layer, said second doped silicon layer having lower and upper surfaces, said lower surface being in contact with the upper surface of said dielectric layer and being substantially conformal thereto. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44)
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Specification