CMOS amplifier with offset adaptation
First Claim
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1. An analog MOS amplifier fabricated as a part of an integrated circuit, said amplifier having a gain of magnitude much larger than 1, including:
- an non-inverting input node,an inverting input node,an output node,a floating node,a first MOS P-channel input transistor, having its gate connected to said non-inverting input node,a second MOS P-channel input transistor, having its gate connected to said floating node,a first current mirror including first and second MOS N-channel transistors, said first MOS N-channel transistor having its drain and gate connected to the drain of said first MOS P-channel input transistor and its source connected to a source of negative voltage, said second MOS N-channel transistor having its gate connected to the gate of said first MOS N-channel transistor, its drain connected to said output node and its source connected to said source of negative voltage,an MOS P-channel bias transistor having its gate connected to a source of bias voltage, its drain connected to the sources of both said first and second MOS P-channel input transistors, and its source connected to a source of positive voltage,a second current mirror including third and fourth MOS N-channel transistors, said third MOS N-channel transistor having its drain and gate connected to the drain of said second MOS P-channel input transistor and its source connected to said source of negative voltage, said fourth MOS N-channel transistor having its gate connected to the gate of said third MOS N-channel transistor and its source connected to said source of negative voltage,a third current mirror including first and second MOS P-channel current mirror transistors, said first MOS P-channel current mirror transistor having its drain and gate connected to the drain of said fourth MOS N-channel transistor, and its source connected to said source of positive voltage, said second MOS P-channel current mirror transistor having its gate connected to the gate of said first MOS P-channel current mirror transistor, its drain connected to said output node and its source connected to said source of positive voltage,a first MOS capacitor having a first electrode connected to said inverting input node and a second electrode connected to said floating node,a second MOS capacitor having a first electrode connected to said output node and a second electrode connected to said floating node,an opaque layer covering portions of the surface of said integrated circuit containing active circuits, said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said second capacitor whereby the offset voltage of said amplifier can be adapted while a source of ultraviolet light is present.
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Abstract
An integrated circuit amplifier having a random input offset voltage is adaptable such that the input offset voltage may be cancelled out. An inverting input node is a floating input node and is coupled to a source of input signal by a first capacitor. A second capacitor is connected between the output of the amplifier and the floating node. An ultraviolet window above the second capacitor allows the floating node to be charged, by the application of ultraviolet light, to a voltage which effectively cancels the input offset voltage. The ultraviolet window and capacitor electrodes are arranged such that the ultraviolet light may strike only the desired areas of the structure.
169 Citations
4 Claims
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1. An analog MOS amplifier fabricated as a part of an integrated circuit, said amplifier having a gain of magnitude much larger than 1, including:
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an non-inverting input node, an inverting input node, an output node, a floating node, a first MOS P-channel input transistor, having its gate connected to said non-inverting input node, a second MOS P-channel input transistor, having its gate connected to said floating node, a first current mirror including first and second MOS N-channel transistors, said first MOS N-channel transistor having its drain and gate connected to the drain of said first MOS P-channel input transistor and its source connected to a source of negative voltage, said second MOS N-channel transistor having its gate connected to the gate of said first MOS N-channel transistor, its drain connected to said output node and its source connected to said source of negative voltage, an MOS P-channel bias transistor having its gate connected to a source of bias voltage, its drain connected to the sources of both said first and second MOS P-channel input transistors, and its source connected to a source of positive voltage, a second current mirror including third and fourth MOS N-channel transistors, said third MOS N-channel transistor having its drain and gate connected to the drain of said second MOS P-channel input transistor and its source connected to said source of negative voltage, said fourth MOS N-channel transistor having its gate connected to the gate of said third MOS N-channel transistor and its source connected to said source of negative voltage, a third current mirror including first and second MOS P-channel current mirror transistors, said first MOS P-channel current mirror transistor having its drain and gate connected to the drain of said fourth MOS N-channel transistor, and its source connected to said source of positive voltage, said second MOS P-channel current mirror transistor having its gate connected to the gate of said first MOS P-channel current mirror transistor, its drain connected to said output node and its source connected to said source of positive voltage, a first MOS capacitor having a first electrode connected to said inverting input node and a second electrode connected to said floating node, a second MOS capacitor having a first electrode connected to said output node and a second electrode connected to said floating node, an opaque layer covering portions of the surface of said integrated circuit containing active circuits, said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said second capacitor whereby the offset voltage of said amplifier can be adapted while a source of ultraviolet light is present. - View Dependent Claims (2, 3)
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4. An adaptive analog MOS inverting amplifier fabricated as a part of an integrated circuit, said amplifier having a gain of magnitude much larger than 1, including:
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an non-inverting input node, an inverting input node, an output node, an amplifying element having a gain larger than 1, including an inverting input, a non-inverting input, and an output, said output connected to said output node, a first floating node, connected to the inverting input of said amplifying element, a first MOS capacitor having a first electrode connected to said inverting input node and a second electrode connected to said first floating node, a second floating node, connected to the non-inverting input of said amplifying element, a second MOS capacitor having a first electrode connected to said non-inverting input node and a second electrode connected to said second floating node, a third MOS capacitor having a first electrode connected to said output node and a second electrode connected to said first floating node, a fourth MOS capacitor having a first electrode connected to said second floating node and a second electrode connected to a source of fixed voltage, the ratio of said third MOS capacitor to said first MOS capacitor being substantially equal to the ratio of said fourth MOS capacitor to said second MOS capacitor, and an opaque layer covering portions of the surface of said integrated circuit containing active circuits, said opaque layer having an aperture therein above said third capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said third capacitor whereby the offset voltage of said adaptive amplifier can be adapted while a source of ultraviolet light is present.
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Specification
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Current AssigneeSynaptics Incorporated
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Original AssigneeSynaptics Incorporated
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InventorsAllen, Timothy P., Mead, Carver A.
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Primary Examiner(s)Mullins, James B.
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Application NumberUS07/486,336Time in Patent Office636 DaysField of Search330/9, 330/253, 330/261, 330/307, 330/308US Class Current330/253CPC Class CodesG06N 3/063 using electronic meansH01L 27/0629 in combination with diodes,...H03F 1/0261 with control of the polaris...H03F 1/303 using a switching device H0...H03F 3/45479 characterised by the way of...H03F 3/45753 using switching means, e.g....H03F 3/45977 using switching means, e.g....
