Hardware implemented moving average processor

• US 5,068,818 A
• Filed: 01/08/1990
• Issued: 11/26/1991
• Est. Priority Date: 06/06/1989
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubushi Denki Kabushiki Kaisha
• Inventors: Uramoto, Shinichi, Terane, Hideyuki
• Primary Examiner(s): Shaw, Dale M.
• Application Number:
  US07/461,966
• Time in Patent Office: 687 Days
• Field of Search: 364/575, 364/734, 364/715.08
• US Class Current: 708/445
• CPC Class Codes: G01R 19/003 Measuring mean values of current or voltage during a given time interval
• CPC Class Codes: G06F 17/18 for evaluating statistical data , e.g. average values, frequency distributions, probability functions, regression analysis forecasting specially adapted for a specific administrative, business or logistic context G06Q10/04
• CPC Class Codes: H03H 17/026 Averaging filters

Abstract

A device for finding a moving average of a signal applied from a signal source includes a first delay circuit for delaying input data sampled in a predetermined sampling period by a time period corresponding to N sampling periods where N is an integer, an accumulator for receiving an output of the first delay circuit and input data to store data of (N-1) terms, and a divider for dividing an output of the accumulator by a coefficient (N-1). The accumulator includes an adder, a second delay circuit for delaying an output of the adder by a time period corresponding to one sampling period, and a subtractor for carrying out subtraction between the output of the first delay circuit and that of the second delay circuit to supply a result of the subtraction to the divider. The adder adds input data and an output of the subtractor. This configuration enables implementation of the device for performing fast moving average processing with a simple configuration.

Claims

1. A device for finding a moving average of a series of data sampled at a predetermined sampling period, comprising:

first delay means for sequentially receiving said series of data and for delaying each of the data by a time period corresponding to N sampling periods to output a result of the delay, N being an integer;

adding means having one input receive sequentially each data of said series of data;

second delay means for delaying an output of said adding means by a time period corresponding to one sampling period to output a result of the delay;

subtracting means for carrying out subtraction between an output of said second delay means and that of said first delay means; and

means for dividing an output of said subtracting means by a coefficient (N-1) to produce a moving average output of said device,

said adding means having the other input receive the output of said subtracting means for adding the data supplied to said one input and said subtracting means output to output a result of the addition.

2. A device according to claim 1, wherein

each said sampled data is formed of a plurality of bits, and

said dividing means comprises means for shifting 3 of the plurality of bits of data from said subtracting means.

3. A device according to claim 2, wherein

said means for shifting comprises

a plurality of data input lines for transmitting therethrough supplied data bits,

a plurality of data output lines provided to intersect with said data input lines,

a plurality of coupling elements, provided at predetermined intersections of said data input lines and said data output lines, each for coupling a corresponding data input line and a corresponding data output line, and

a plurality of control signal lines provided in a direction of intersecting with said data input lines and said data output lines for selectively activating said plurality of coupling elements.

4. A device for finding a moving average of a series of data sampled at a predetermined sampling period, comprising:

first delay means for sequentially receiving said series of data and for delaying each of the data by a time period corresponding to N sampling periods to output a result of the delay, N being an integer, wherein said first delay means comprises a plurality of cascade-connected delay circuit means;

adding means having one input receive sequentially each data of said series of data;

second delay means for delaying an output of said adding means by a time period corresponding to one sampling period to output a result of the delay;

subtracting means for carrying out subtraction between an output of said second delay means and an output of said first delay means, said adding means having the other input receive the output of said subtracting means for adding the data supplied to said one input and said subtracting means output to output a result of the addition;

means for dividing an output of said subtracting means by a coefficient (N-1) to produce a moving average output of said device;

selecting means for selectively passing one output from said plurality of cascade-connected delay circuit means to said subtracting means, and

control means responsive to a moving average term number instructing signal for generating a signal for defining a selecting operation of said selecting means and a division coefficient for said dividing means.

5. A device according to claim 4, wherein

said moving average term number instructing signal is externally applied.

6. A device according to claim 4, wherein

said control means comprises

means for monitoring the moving average output of said device, and

means responsive to an output of said monitor means for generating said moving average term number instructing signal.

7. A system for digitally processing an analog signal applied from a signal source, comprising:

means for sampling the analog signal from said signal source at a predetermined sampling period to convert the sampled signal into digital signal data;

moving average processing means for carrying out moving average processing on an output of said converting means to produce a moving average output; and

means for carrying out predetermined data processing of said moving average output,

said moving average processing means comprising

first delay means for receiving output data of said converting means in series and delaying the received data by a time period corresponding to N sampling periods to output the delayed data, N being an integer,

adding means having one input receive the output data of said converting means in series,

second delay means for delaying an output of said adding means by a time period corresponding to one sampling period to output a result of the delay,

means for carrying out subtraction between an output of said second delay means and that of said first delay means, and

means for dividing an output of said subtracting means by a coefficient (N-1) to produce said moving average output,

said adding means having the other input receive the output of said subtracting means, and adding the data supplied to said one input and said subtracting means output to output a result of the addition.

8. A system of claim 7, further comprising

buffer means provided between said converting means and said moving average processing means for adjusting an operation speed of said converting means and that of said moving average processing means to each other.

9. A system of claim 7, further comprising

buffer means provided between said moving storage processing means and said data processing means for adjusting a processing speed of said moving average processing means and that of said data processing means to each other.

10. A method of finding a moving average of a series of data sampled at a predetermined sampling period, comprising the steps of:

delaying each of the data in said series of data by a time period corresponding to N sampling periods, N being an integer;

performing adding operation on the data delayed by the time period corresponding to said N sampling periods;

delaying the data added in said adding step by a time period corresponding to one sampling period;

performing subtracting operation between the data delayed by the time period corresponding to said N sampling periods and the data delayed by the time period corresponding to said one sampling period; and

dividing data obtained in said subtracting step by a coefficient (N-1),

said adding step comprising the step of adding the data obtained in said subtracting step and the data delayed by the time period corresponding to said N sampling periods.

11. A method of claim 11, wherein

each data of said series of data is represented in a plurality of bits, and

said dividing step comprises the step of shifting each bit of supplied data in a direction of the least significant bit.