Floating point apparatus with concurrent input/output operations
First Claim
1. In a data processing system, a method for performing a series of operation sequences in a plurality of contiguous general purpose registers and an arithmetic logic unit and providing a final result to an information bus for each operation sequence, said method comprising the steps of:
- assigning each of said plurality of contiguous general purpose registers to uniquely store parameters, intermediate results of operations in the sequence and a final operation sequence result;
computing results in said arithmetic logic unit for each of said sequence operations in the series consecutively;
storing results from each sequence operation in its assigned register after each sequence operation computation; and
outputting to said information bus the final operation sequence result from its assigned register of a preceding sequence simultaneously with the computation of a next sequence operation result in its assigned register.
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Abstract
In a data processing system, a method for performing a series of operation sequence results and providing such results including the steps of (1) computing the results for each sequence of operations consecutively and (2) reading the results for the proceeding computations during the computation of a current operation result. This method further includes the use of registers for the temporary storage of the sequence results. During the computation of the operation sequence results, other registers are used in performing the sequence operations. The operations store parameters in a progressive fashion. In other words, the initial operations are performed in one set of registers while the final result from the sequence operation is stored in a different register. The result of a previous operation sequence computation is read from a register that is not being used during the computation of the current sequence operation. Also, included is an interlock capability to prevent the storing of sequence in registers that are concurrently being read.
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Citations
28 Claims
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1. In a data processing system, a method for performing a series of operation sequences in a plurality of contiguous general purpose registers and an arithmetic logic unit and providing a final result to an information bus for each operation sequence, said method comprising the steps of:
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assigning each of said plurality of contiguous general purpose registers to uniquely store parameters, intermediate results of operations in the sequence and a final operation sequence result; computing results in said arithmetic logic unit for each of said sequence operations in the series consecutively; storing results from each sequence operation in its assigned register after each sequence operation computation; and outputting to said information bus the final operation sequence result from its assigned register of a preceding sequence simultaneously with the computation of a next sequence operation result in its assigned register. - View Dependent Claims (2, 3, 4, 5, 6, 9, 10, 11)
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7. In a data processing system, a method for performing a series of operation sequences in a plurality of contiguous general purpose registers and an arithmetic logic unit and providing a final result to an information bus for each operation sequence, said method comprising the steps of:
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assigning each of said plurality of contiguous general purpose registers to uniquely store parameters, intermediate results of operations in the sequence and a final operation sequence result; storing parameters for an initial sequence operation computation to registers assigned to store the parameters; computing results in said arithmetic logic unit for each of said sequence operations in the series consecutively; storing results from each sequence operation in its assigned register after each sequence operation computation; and storing parameters from said information bus for a next sequence operation computation to its assigned register simultaneously with computation of a current sequence operation result in its assigned register. - View Dependent Claims (8)
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12. A data processing system comprising:
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an information bus; an information bus interface means for input and output of information with the information bus; a plurality of contiguous general purpose registers; a computational unit; data transfer means connected to said information bus interface means, said plurality of registers and said computational unit for transferring data therebetween; and control means connected to said information bus interface means, said plurality of registers, said computational unit, and said data transfer means for performing a current one of a series of computational sequences in said computational unit and a first portion from said plurality of registers while simultaneously outputting a result of a previous series from at least one of a second portion of said plurality of registers to said information bus. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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21. A data processing system comprising:
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an information bus; an information bus interface means for input and output of information with the information bus; a plurality of contiguous general purpose registers; a computational unit; data transfer means connected to said information bus interface means, said plurality of registers and said computational unit for transferring data therebetween; and control means connected to said information bus interface means, said plurality of registers, said computational unit, and said data transfer means for performing a current one of a series of computational sequence operations in said computational unit and a first portion of said plurality of registers while storing parameters for a next sequence operation computation to a register of a second portion of said plurality of registers during computation of said current sequence operation in said computational unit. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28)
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Specification