Floating point apparatus with concurrent input/output operations

• US 5,068,819 A
• Filed: 01/24/1991
• Issued: 11/26/1991
• Est. Priority Date: 06/23/1988
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Misra, Mamata, Vanover, Michael T., Urquhart, Robert J., Voltin, John A.
• Primary Examiner(s): Shaw, Dale M.
• Assistant Examiner(s): Mai, Tan V.
• Application Number:
  US07/647,183
• Time in Patent Office: 306 Days
• Field of Search: 364/748, 364/736, 364/200, 364/900
• US Class Current: 708/520
• CPC Class Codes: G06F 15/8084 Special arrangements thereof, e.g. mask or switch

Abstract

In a data processing system, a method for performing a series of operation sequence results and providing such results including the steps of (1) computing the results for each sequence of operations consecutively and (2) reading the results for the proceeding computations during the computation of a current operation result. This method further includes the use of registers for the temporary storage of the sequence results. During the computation of the operation sequence results, other registers are used in performing the sequence operations. The operations store parameters in a progressive fashion. In other words, the initial operations are performed in one set of registers while the final result from the sequence operation is stored in a different register. The result of a previous operation sequence computation is read from a register that is not being used during the computation of the current sequence operation. Also, included is an interlock capability to prevent the storing of sequence in registers that are concurrently being read.

Claims

1. In a data processing system, a method for performing a series of operation sequences in a plurality of contiguous general purpose registers and an arithmetic logic unit and providing a final result to an information bus for each operation sequence, said method comprising the steps of:

assigning each of said plurality of contiguous general purpose registers to uniquely store parameters, intermediate results of operations in the sequence and a final operation sequence result;

computing results in said arithmetic logic unit for each of said sequence operations in the series consecutively;

storing results from each sequence operation in its assigned register after each sequence operation computation; and

outputting to said information bus the final operation sequence result from its assigned register of a preceding sequence simultaneously with the computation of a next sequence operation result in its assigned register.

2. A method according to claim 1 wherein each operation sequence includes a plurality of arithmetic operations that are identical for the operation sequences of said series.

3. A method according to claim 2 wherein each operation result is stored in said storing step in a unique one of said registers during the computation of the sequence.

4. A method according to claim 3 wherein said step of computing results includes pipeline computing said results for a plurality of sequences operations.

5. A method according to claim 4 wherein said computing step includes the step of providing parameters to registers for the computation of sequence operation before said results of the sequence are computed.

6. A method according to claim 5 wherein said outputting step includes the step of preventing the current computation operation from accessing the register to store the final results until the results from the previous operation has been output.

9. A method according to claim 5 wherein each operation result is stored in said storing step in a unique one of said registers during the computation of the sequence.

10. A method according to claim 9 wherein said step of computing results includes pipeline computing said results for a plurality of sequences operations.

11. A method according to claim 10 wherein said step of storing parameters to assigned registers for a next sequence operation includes the step of preventing the access of a register for storing said parameters until the current operation sequence operation has completed access to that register.

7. In a data processing system, a method for performing a series of operation sequences in a plurality of contiguous general purpose registers and an arithmetic logic unit and providing a final result to an information bus for each operation sequence, said method comprising the steps of:

assigning each of said plurality of contiguous general purpose registers to uniquely store parameters, intermediate results of operations in the sequence and a final operation sequence result;

storing parameters for an initial sequence operation computation to registers assigned to store the parameters;

computing results in said arithmetic logic unit for each of said sequence operations in the series consecutively;

storing results from each sequence operation in its assigned register after each sequence operation computation; and

storing parameters from said information bus for a next sequence operation computation to its assigned register simultaneously with computation of a current sequence operation result in its assigned register.

8. A method according to claim 7 wherein each operation sequence includes a plurality of arithmetic operations that are identical for the operation sequences of said series.

12. A data processing system comprising:

an information bus;

an information bus interface means for input and output of information with the information bus;

a plurality of contiguous general purpose registers;

a computational unit;

data transfer means connected to said information bus interface means, said plurality of registers and said computational unit for transferring data therebetween; and

control means connected to said information bus interface means, said plurality of registers, said computational unit, and said data transfer means for performing a current one of a series of computational sequences in said computational unit and a first portion from said plurality of registers while simultaneously outputting a result of a previous series from at least one of a second portion of said plurality of registers to said information bus.

13. A data processing system according to claim 12 wherein said control means further includes means for assigning registers of said plurality of registers to store parameters, intermediate results of operations in the sequence and a final operation sequence result, means for computing results in said computational unit for each of the series of operation sequences consecutively by computing results for each of said sequence operations in the series consecutively, means for storing results from each sequence operation in an assigned register of said plurality of registers after each operation sequence computation and means for outputting a final operation sequence result from its assigned register of a preceding sequence simultaneously during computation of a current sequence operation result.

14. A data processing system according to claim 13 wherein said control means further includes means for storing parameters for a next sequence operation computation to its assigned register of said plurality of registers during computation of a current sequence operation result.

15. A data processing system according to claim 14 wherein each operation sequence includes a plurality of arithmetic operations that are identical for the operation sequences of said series.

16. A data processing system according to claim 15 wherein said control means includes means for storing each operation result in a unique one of said registers during the computation of the sequence.

17. A data processing system according to claim 16 wherein said control means includes means for pipeline computing said results for a plurality of sequences operations in said computational unit and said plurality of registers.

18. A data processing system according to claim 17 wherein said control means includes means for storing parameters to assigned ones of said plurality of registers for the computation of sequence operation before said results of the sequence are computed.

19. A data processing system according to claim 18 wherein said control means includes means for preventing the current computation operation from accessing the register to store the final results until the results from the previous operation has been output.

20. A data processing system according to claim 19 further including a system processor means connected to said information bus for providing commands to said control means for performing said computational sequence operations.

21. A data processing system comprising:

an information bus;

an information bus interface means for input and output of information with the information bus;

a plurality of contiguous general purpose registers;

a computational unit;

data transfer means connected to said information bus interface means, said plurality of registers and said computational unit for transferring data therebetween; and

control means connected to said information bus interface means, said plurality of registers, said computational unit, and said data transfer means for performing a current one of a series of computational sequence operations in said computational unit and a first portion of said plurality of registers while storing parameters for a next sequence operation computation to a register of a second portion of said plurality of registers during computation of said current sequence operation in said computational unit.

22. A data processing system according to claim 21 wherein said control means further includes means for assigning registers of said plurality of registers to store parameters, intermediate results of operations in the sequence and a final operation sequence result, means for computing results in said computational unit for each of the series of operation sequences consecutively by computing results for each of said sequence operations in the series consecutively, means for storing results from each sequence operation in its assigned register of said plurality of registers after each sequence operation computation and means for outputting a final operation sequence result from its assigned register of a preceding sequence simultaneously during computation of a current sequence operation result.

23. A data processing system according to claim 22 wherein each operation sequence includes a plurality of arithmetic operations that are identical for the operation sequences of said series.

24. A data processing system according to claim 23 wherein said control means includes means for storing each operation result in a unique one of said registers during the computation of the sequence.

25. A data processing system according to claim 24 wherein said control means includes means for pipeline computing said results for a plurality of sequences operations in said computational unit and said plurality of registers.

26. A data processing system according to claim 25 wherein said control means includes means for storing parameters to assigned ones of said plurality of registers for the computation of sequence operation before said results of the sequence are computed.

27. A data processing system according to claim 26 wherein said control means includes means for preventing the current computation operation from accessing the register to store the final results until the results from the previous operation has been output.

28. A data processing system according to claim 27 further including a system processor means connected to said information bus for providing commands to said control means for performing said computational sequence operations.